DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claims 8 and 18 are objected to because of the following informalities: in each of claims 8 and 18, “the first side of the first side of the substrate” should be changed to “the first side of the substrate” for readability.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1, 7 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sarig et al. U.S. Patent Application Publication 2004/0036363 A1 (the ‘363 reference).
The reference discloses in Figs. 4-5 and related text a semiconductor device as claimed.
Referring to claim 1, the ‘363 reference discloses a semiconductor device comprising:
a semiconductor substrate (401, para [27] (paragraph(s) [0027])) having a first protected circuit (P0, para ]27]);
a first guard ring (440, para [29]); and
a second guard ring (420/430, para [28]) adjacent to the first guard ring (440) and around the first protected circuit (P0),
wherein the second guard ring (420/430) includes:
a first via tower (left via tower 420) configured to provide a first reference voltage (VDD, para [28]);
a second via tower (430) configured to provide a second reference voltage (GND, para [28]) different than the first reference voltage (the VDD); and
at least a third via tower (right via tower 420) configured to provide the first reference voltage (the VDD).
Referring to claim 7 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses an integrated circuit (IC) device comprising:
a substrate (440);
a first protected circuit (P0) on a first side of the substrate; and
a guard ring (420/430) around the first protected circuit, the guard ring including:
a first via tower (left via tower 420) on the first side of the substrate and configured to provide a first reference voltage (VDD);
a second via tower (430) on the first side of the substrate and configured to provide a second reference voltage (GND) different than the first reference voltage; and
a third via tower (right via tower 420) on the first side of the substrate and configured to provide the first reference voltage (the VDD).
Referring to claim 17 and using the same reference characters, interpretations, and citations as detailed above for claims 1 and 7 where applicable, the reference discloses a method of fabricating a semiconductor device, the method comprising:
forming a first protected circuit (P0) on a first side of a semiconductor substrate (440); and
forming a guard ring (420/430) around the first protected circuit, the forming a guard ring including:
forming a first via tower (left via tower 420) on the first side of the semiconductor substrate and configured to provide a first reference voltage;
forming a second via tower (430) on the first side of the semiconductor substrate and configured to provide a second reference voltage (GND) different than the first reference voltage; and
forming a third via tower (right via tower 420) on the first side of the semiconductor substrate (440) and configured to provide the first reference voltage (the VDD).
Allowable Subject Matter
4. Claims 2-6, 8-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor device, an integrated circuit (IC) device and a method of fabricating a semiconductor device with all exclusive limitations as recited in claims 2, 4, 5, 6, 8, 11, 12, 15, 18 and 20, which may be characterized (claim 2) in that a buried power grid (BPG) is beneath the semiconductor substrate and in that the second guard ring includes at least a portion of the BPG, (claim 8) a buried power grid (BPG) is on a second side of the substrate, and in that the guard ring includes at least a portion of the BPG, (claim 18) in forming a buried power grid (BPG) on a second side of the semiconductor substrate, and in that the guard ring is formed to include at least a portion of the BPG, (claim 4) the fourth via tower is aligned with the first via tower along a direction normal to the semiconductor substrate, (claims 5 and 11) in that the first via tower forms at least a portion of the non-BPG, (claim 6) in that the second protected circuit includes a transistor driver array, (claim 12) the sixth via tower is between the fourth via tower and the fifth via tower relative to a second direction, (claim 15) the seventh via tower is between the fourth via tower and the fifth via tower relative to a second direction, and in that the fourth via tower is aligned with the seventh via tower along the first direction, and (claim 20) the fourth via tower and the seventh via tower are configured to provide an input/output signal.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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08-18-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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