DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 7/22/2026 has been fully considered and is found persuasive. Examiner appreciates the explanation provided to clarify the interpretation that claims 1 and 10 should be given. The rejection below is being provided in light of the clarifying information provided.
Applicant argues on page 7 that Sawabe’s sidewalls of upper container 164 are directly over and colinear with sidewalls of second container 163. Base portion of 164 projects only over inner fill material 161 therefore does not teach the claim limitations of claim 1.
Examiner respectfully disagrees. the claims merely recites that the laterally opposing projections are elevationally over tops of the second container. The material of the projections are not specified. As rejected below, the first container is now specified as 165, and material layer 164 which has projections which projects radially inward is elevationally over the second container 163. Therefore, each and every limitation is met by Lee and Sawabe.
The rejection has been updated below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: claim 1 (and their dependent claims) recites the limitation “laterally opposing projections that project radially inward” recited at the last two lines of claim 1 lacks structural relationship as to what the laterally opposing projections are. The remarks filed 7/22/2026 on page 6, middle paragraph, states the same limitation but does not clarify what the projections are.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 and 10 (and their dependent claims) recites the limitation “the alternating tiers of the different composition insulating materials in the second region” at lines 14-15 of claim 1 and at lines 14-15 of claim 10. It is unclear as to what element said limitation is referring to.
Claim 1 further recites “a conductive via” at line 2 and line 12. It is unclear as to whether the two recitations are the same or different materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, and 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US PGPub 2017/0338241) in view of Sawabe et al. (US PGPub 2017/0077120; hereinafter “Sawabe”).
Re claim 1: Lee teaches (e.g. fig. 4) a memory circuitry comprising a vertical string of memory cells (MC) and a conductive via (193B), comprising: a first region (left segment of fig. 4; hereinafter “1R”) of vertically-alternating tiers of first insulative material (151) and control gate material (171G), a second region (right segment of fig. 4; hereinafter “2R”) of vertically-alternating tiers of the first insulative material (151) and a second insulative material (153), the second region (2R) being laterally offset from the first region (1R); a channel pillar (167; e.g. paragraph 55) extending elevationally through multiple of the vertically-alternating tiers (151, 171G) within the first region (1R); tunnel insulator (165; e.g. paragraph 57), charge storage material (163; e.g. paragraph 57), and control gate blocking insulator (161; e.g. paragraph 57) between the channel pillar (167) and the control gate material (171G) of individual of the tiers of the control gate material (167G) within the first region (1R); a conductive via (193B) extending elevationally through the vertically- alternating tiers (151, 153) in the second region (2R), the conductive via (193B) within the alternating tiers (151, 153) of the different composition insulating materials (silicon oxide 151 and silicon nitride 153; e.g. paragraph 85) in the second region (2R).
Lee is silent as to explicitly teaching the conductive via comprising a second conductive container inside a first conductive container within the alternating tiers of the different composition insulating materials in the second region, the first and second conductive containers individually having opposing sidewalls and a base extending there-between in vertical cross-section; and laterally opposing projections that project radially inward toward one another elevationally over tops of the second container sidewalls.
Sawabe teaches (e.g. fig. 5) the conductive via (via formed of metal layers 161,163,162,164,165; hereinafter “CV”) comprising a second conductive container (163) inside a first conductive container (165) within the alternating tiers of the different composition insulating materials (151, 153 of Lee) in the second region (2R of Lee), the first (165) and second (163) conductive containers individually having opposing sidewalls and a base (base of 163, 165) extending there-between in vertical cross-section; and laterally opposing projections (base of 164) that project radially inward toward one another elevationally over tops of the second container (163) sidewalls.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the via structure of Sawabe in the device of Lee in order to have the predictable result of using a known structure which has superior diffusion prevention properties so that via integrity is improved.
Re claim 2: Lee teaches claim the memory circuitry of claim 1 wherein the first region (1R) is over a conductive structure (SR) and the second region (2R) is over an insulator structure (147, 129).
Re claim 3: Lee teaches claim the memory circuitry of claim 2 wherein the conductive structure (SR) comprises a conductively doped source material (source stack SR).
Re claim 6: Lee teaches claim the memory circuitry of claim 2 wherein the channel pillar (167) contacts the conductive structure (SR).
Re claim 7: Lee teaches claim the memory circuitry of claim 2 wherein the conductive via (193B) extends entirely through the insulator structure (147).
Re claim 8: Lee teaches claim the memory circuitry of claim 7 further comprising a conductive region (119) under the insulator structure (147) and wherein the conductive via (193B) extends to an upper surface of the conductive region (119).
Re claim 9: Lee teaches claim the memory circuitry of claim 8 wherein the conductive region (119) comprises one or more materials selected from the group consisting of conductively doped semiconductive material, an elemental metal, a mixture of two or more elemental metals, an alloy of two or more elemental metals, and conductive metal compounds (resistor conductive layer for 119; e.g. paragraph 77).
Re claim 10: Lee teaches (e.g. fig. 4) memory circuitry comprising a vertical string of memory cells (MC) and a conductive via (193B), comprising: a first region (left segment of fig. 4; hereinafter “1R”) of vertically-alternating tiers of first insulative material (151) and control gate material (171G), a second region (right segment of fig. 4; hereinafter “2R”) of vertically-alternating tiers of the first insulative material (151) and a second insulative material (153), the second region (2R) being laterally offset from the first region (1R); a channel pillar (167; e.g. paragraph 55) extending elevationally through multiple of the vertically-alternating tiers (151,171G) within the first region (1R); tunnel insulator (165; e.g. paragraph 57), charge storage material (163; e.g. paragraph 57), and control gate blocking insulator (161; e.g. paragraph 57) between the channel pillar (167) and the control gate material (171G) of individual of the tiers of the control gate material (167G) within the first region (1R); and a conductive via (193B) extending elevationally through the vertically- alternating tiers (151, 153) in the second region (2R).
Lee is silent as to explicitly teaching the conductive via comprising a conductive container within the alternating tiers of the different composition insulating materials in the second region, the conductive container having opposing sidewalls and a base extending there-between in vertical cross- section, elevationally uppermost portions of the opposing sidewalls having a first lateral thickness that is less than a second lateral thickness of a lower portion of the opposing sidewalls immediately above the base in the vertical cross-section.
Sawabe teaches (e.g. fig. 5) the conductive via (via formed of metal layers 161,163,162,164,165; hereinafter “CV”) comprising a conductive container (165,163) within the alternating tiers of the different composition insulating materials (151, 153 of Lee) in the second region (2R of Lee), the conductive container (165,163) having opposing sidewalls (sidewalls of 165,163) and a base (base of 165,163) extending there-between in vertical cross- section, elevationally uppermost portions of the opposing sidewalls (sidewalls of 165) having a first lateral thickness (thickness of 165; hereinafter “1T”) that is less than a second lateral thickness (thickness of 165,163; hereinafter “2T”) of a lower portion of the opposing sidewalls (sidewalls of 165,163) immediately above the base (base of 165,163) in the vertical cross-section
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the via structure of Sawabe in the device of Lee in order to have the predictable result of using a known structure which has superior diffusion prevention properties so that via integrity is improved.
Re claim 11: Lee in view of Sawabe teaches the memory circuitry of claim 10 wherein the first lateral thickness (1T of Sawabe) is less than or equal to half (1T is half the thickness of 2T of Sawabe) the second lateral thickness (2T of Sawabe).
Claim(s) 4, 5, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Sawabe, as applied to claim 2, and further in view of Kidoh et al. (US PGPub 2009/0212350; hereinafter “Kidoh”).
Re claim 4: Lee in view of Sawabe teaches substantially the entire structure of claim 2 except explicitly teaching the memory circuitry wherein the conductive structure (SR of Lee) comprises conductively doped polysilicon over a layer of tungsten silicide.
Kidoh teaches (e.g. fig. 4) the conductive structure (SR of Lee) comprises conductively doped polysilicon (source-side conductive layer 22 formed of P+ polysilicon; e.g. paragraph 55) over a layer of tungsten silicide (source-side metal layer 23 formed of WSi; e.g. paragraph 55).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results to use the conductive structure as taught by Kidoh in the device of Lee in view of Sawabe in order to have the predictable result of using a known structure which can improve the conduction performance of the memory device of Lee which would ensure highly conductive common source region for the memory device of Lee.
Re claim 5: Lee in view of Sawabe and Kidoh teaches the memory circuitry of claim 4 wherein the conductively doped polysilicon (22 of Kidoh) has a thickness of about 500 Angstroms (there exists within 22 a thickness of 50nm) and the tungsten silicide (23 of Kidoh) has a thickness of about 900 Angstroms (there exists within 23 a thickness of 90nm).
Re claim 12: Lee in view of Sawabe teaches substantially the entire structure of claim 10 except explicitly teaching the memory circuitry wherein the channel pillar (167 of Lee) extends into a source material (141, 185 of Lee) comprising conductively doped polysilicon and tungsten silicide.
Kidoh teaches (e.g. fig. 4) the memory circuitry wherein the channel pillar (167 of Lee) extends into a source material (141, 185 of Lee) comprising conductively doped polysilicon (source-side conductive layer 22 formed of P+ polysilicon; e.g. paragraph 55) and tungsten silicide (source-side metal layer 23 formed of WSi; e.g. paragraph 55).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results to use the conductive structure as taught by Kidoh in the device of Lee in view of Sawabe in order to have the predictable result of using a known structure which can improve the conduction performance of the memory device of Lee which would ensure highly conductive common source region for the memory device of Lee.
Re claim 13: Lee in view of Sawabe teaches the memory circuitry of claim 12 wherein the channel pillar (167 of Lee) comprises a doped semiconductor material (dopant supplied to the silicon layer of channel layer 167; e.g. paragraph 51) that extends continuously from an upper surface of the channel pillar (167 of Lee) to a bottom surface of the channel pillar (167 of Lee) in direct physical contact with the source material (SR of Lee).
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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