DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 3 as shown in fig. 22 (claims 1-13 readable thereon) in the reply filed on 4/27/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “laterally opposing projections that project radially inward toward one another elevationally over tops of the second container sidewalls” at the last two lines. The specification as filed recites that elements 74 and 76 are projections that project over tops of second container 46 at paragraph 55. However, the claimed “second conductive container (69) inside a first conductive container (46)” means that element 46 corresponds to the claimed “first conductive container”, therefore the claimed projections (74,76) over tops of the second container (69) is not supported by the specification, but rather the claimed projections (74, 76) are over tops of the first container (46). These features are not disclosed in the elected embodiment of fig. 22.
Claim 10 recites the limitation “uppermost portions of the opposing sidewalls having a first lateral thickness that is less than a second lateral thickness of a lower portion of the opposing sidewalls immediately above the base in the vertical cross-section” at the last 4 lines. There is no disclosure of the conductive container sidewall which has a lateral thickness immediately above the base being thicker than a lateral thickness at the uppermost portions of the conductive sidewall. The elected embodiment of fig. 22 only shows a thicker sidewall at projections 74, 76 but that area is not immediately above the base.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US PGPub 2017/0338241) in view of Sawabe et al. (US PGPub 2017/0077120; hereinafter “Sawabe”).
Re claim 1: Lee teaches (e.g. fig. 4) a memory circuitry comprising a vertical string of memory cells (MC) and a conductive via (193B), comprising: a first region (left segment of fig. 4; hereinafter “1R”) of vertically-alternating tiers of first insulative material (151) and control gate material (171G), a second region (right segment of fig. 4; hereinafter “2R”) of vertically-alternating tiers of the first insulative material (151) and a second insulative material (153), the second region (2R) being laterally offset from the first region (1R); a channel pillar (167; e.g. paragraph 55) extending elevationally through multiple of the vertically-alternating tiers (151, 171G) within the first region (1R); tunnel insulator (165; e.g. paragraph 57), charge storage material (163; e.g. paragraph 57), and control gate blocking insulator (161; e.g. paragraph 57) between the channel pillar (167) and the control gate material (171G) of individual of the tiers of the control gate material (167G) within the first region (1R); a conductive via (193B) extending elevationally through the vertically- alternating tiers (151, 153) in the second region (2R), the conductive via (193B) within the alternating tiers (151, 153) of the different composition insulating materials (silicon oxide 151 and silicon nitride 153; e.g. paragraph 85) in the second region (2R).
Lee is silent as to explicitly teaching the conductive via comprising a second conductive container inside a first conductive container within the alternating tiers of the different composition insulating materials in the second region, the first and second conductive containers individually having opposing sidewalls and a base extending there-between in vertical cross-section; and laterally opposing projections that project radially inward toward one another elevationally over tops of the second container sidewalls.
Sawabe teaches (e.g. fig. 5) the conductive via (via formed of metal layers 161,163,162,164,165; hereinafter “CV”) comprising a second conductive container (163) inside a first conductive container (165, 164) within the alternating tiers of the different composition insulating materials (151, 153 of Lee) in the second region (2R of Lee), the first (165, 164) and second (163) conductive containers individually having opposing sidewalls and a base (base of 163, 165) extending there-between in vertical cross-section; and laterally opposing projections (base of 164) that project radially inward toward one another elevationally over tops of the second container (163) sidewalls.
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the via structure of Sawabe in the device of Lee in order to have the predictable result of using a known structure which has superior diffusion prevention properties so that via integrity is improved.
Re claim 2: Lee teaches claim the memory circuitry of claim 1 wherein the first region (1R) is over a conductive structure (SR) and the second region (2R) is over an insulator structure (147, 129).
Re claim 3: Lee teaches claim the memory circuitry of claim 2 wherein the conductive structure (SR) comprises a conductively doped source material (source stack SR).
Re claim 6: Lee teaches claim the memory circuitry of claim 2 wherein the channel pillar (167) contacts the conductive structure (SR).
Re claim 7: Lee teaches claim the memory circuitry of claim 2 wherein the conductive via (193B) extends entirely through the insulator structure (147).
Re claim 8: Lee teaches claim the memory circuitry of claim 7 further comprising a conductive region (119) under the insulator structure (147) and wherein the conductive via (193B) extends to an upper surface of the conductive region (119).
Re claim 9: Lee teaches claim the memory circuitry of claim 8 wherein the conductive region (119) comprises one or more materials selected from the group consisting of conductively doped semiconductive material, an elemental metal, a mixture of two or more elemental metals, an alloy of two or more elemental metals, and conductive metal compounds (resistor conductive layer for 119; e.g. paragraph 77).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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