DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-10, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10121739 B1 Kirby et al hereafter “Kirby”.
Claim 1 Kirby teaches an apparatus of a ferromagnetic power transformer in a 3D integrated circuit, the apparatus comprising:
a power transmission semiconductor chip stacked within the 3D integrated circuit, wherein the power transmission semiconductor chip comprises (600 and/or 700 fig. 6-7, Column 8 lines 37-50 sufficiently discloses the structure as of 300 fig. 3 which is substantially identical to the device of fig. 6-7 as operable as a power transformer in “operating the device 300 as a power transformer”):
a first substrate (comprising 621a fig. 6);
a plurality of first dielectric layers (comprising 621b fig. 6, note an embodiment of the process making of 621b is illustrated fig.9B-9D as 902 and it is formed from at least 3 layering steps and/or 3 integral layers although it is not explicitly illustrated as 3 independent dielectric layers);
a plurality of first metal layers (comprising 623, 624a, and 624b fig. 6), wherein an individual first metal layer of the plurality of first metal layers is in an individual first dielectric layer of the plurality of first dielectric layers over the first substrate [sufficiently illustrated fig. 6];
a first inductive coil (623 fig. 6) in the individual first metal layer of the plurality of first metal layers, wherein the first inductive coil is to wirelessly transmit AC power signals [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed]; and
a power transmission circuit coupled to the first inductive coil, wherein the power transmission circuit includes a DC to AC converter to convert first DC power signals to the AC power signals [sufficiently discloses “operably connected to other circuit elements” column 11 lines 60-65, wherein “other circuit elements (not shown), including one or more rectifiers to revert a coupled alternating current to DC and one or more capacitors or other filter elements to provide steady current” Column 9 lines 40-45 as the embodiment of 400 fig. 4 is substantially similar to the embodiment of 600 fig. 6, in view of this the current starts as DC converted to AC power-coupled and/or transformed through the device of fig. 6 and reverted and/or converted back to DC by the “other circuit elements” operably connected];
a plurality of power reception semiconductor chips (610 fig. 6) overlapping the power transmission semiconductor chip [sufficiently illustrated fig. 6], wherein an individual power reception semiconductor chip of the plurality of power reception semiconductor chips wirelessly receives the AC power signals from the power transmission semiconductor chip, wherein the individual power reception semiconductor chip comprises [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed] :
a second substrate (611a fig. 6);
a plurality of second dielectric layers (611b fig. 6, note an embodiment of the process making of 611b is illustrated fig.9B-9D as 902 and it is formed from at least 3 layering steps and/or 3 integral layers although it is not explicitly illustrated as 3 independent dielectric layers);
a plurality of second metal layers (comprising 613, 614a, 614b fig. 6), wherein an individual second metal layer of the plurality of second metal layers is in an individual second dielectric layer of the plurality of second dielectric layers over the second substrate [sufficiently illustrated fig. 6];
a second inductive coil (613 fig. 6) in the individual second metal layer of the plurality of second metal layers [sufficiently illustrated fig. 6], wherein the second inductive coil is to wirelessly receive the AC power signals from the first inductive coil [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed]; and
a power reception circuit coupled to the second inductive coil, wherein the power reception circuit includes an AC to DC converter to convert the AC power signals to second DC power signals [sufficiently discloses “operably connected to other circuit elements” column 11 lines 40-45, wherein “other circuit elements (not shown), including one or more rectifiers to revert a coupled alternating current to DC and one or more capacitors or other filter elements to provide steady current” Column 9 lines 40-45 as the embodiment of 400 fig. 4 is substantially similar to the embodiment of 600 fig. 6, in view of this the current starts as DC converted to AC power-coupled and/or transformed through the device of fig. 6 and reverted and/or converted back to DC by the “other circuit elements” operably connected]; and
a ferromagnetic through silicon via (comprising TSV 612a, 615a, and 622a fig. 6, wherein the TSVs are sufficiently disclosed as comprising ferromagnetic materials “nickel, iron, cobalt, niobium, or an alloy thereof” column 5 lines 49-52 ) substantially in a center of the first inductive coil and the second inductive coil [sufficiently illustrated fig. 6], wherein the ferromagnetic through silicon via provides a wireless power transfer channel to enable the wireless transfer of the AC power signals between the power transmission semiconductor chip and the plurality of power reception semiconductor chips at one or more frequencies [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed].
Claim 3 Kirby teaches as shown above the apparatus of claim 1, wherein a shape of a cross-section of the individual ferromagnetic through silicon via comprises one of a rectangular shape, a square shape, a hexagonal shape, an octagonal shape, a circular shape, an elliptical shape, or any combination thereof [sufficiently disclosed and/or illustrated as elliptical fig. 2, 8].
Claim 4 Kirby teaches as shown above the apparatus of claim 1, wherein the first inductive coil of the power transmission semiconductor chip and the second inductive coil of the individual power reception semiconductor chip comprise one of a rectangular shape, a square shape, a circular shape, a hexagonal shape, or any combination thereof [sufficiently disclosed and/or illustrated as rectangular fig. 2, 8].
Claim 5 Kirby teaches as shown above the apparatus of claim 1, wherein transmission and reception of the AC power signals through the wireless power transfer channel protects the wireless power transfer channel against electromigration [met under MPEP 2112.01 the device is materially and/or structurally the same as disclosed thus property and/or function is presumed].
Claim 6 Kirby teaches as shown above the apparatus of claim 1, wherein the first inductive coil of the power transmission semiconductor chip and the second inductive coil of the individual power reception semiconductor chip communicate in microwave, mm-wave, and/or terra hertz (THz) communication bands through the wireless power transfer channel [met under MPEP 2112.01 the device is materially and/or structurally the same as disclosed thus property and/or function is presumed].
Claim 7 Kirby teaches an apparatus of a ferromagnetic transformer in a 3D integrated circuit, the apparatus comprising:
a plurality of semiconductor chips (comprising 610 and 620, “multi-die semiconductor” column 2 lines 25-30) stacked within the 3D integrated circuit, wherein an individual semiconductor chip of the plurality of semiconductor chips comprises:
a substrate (621a and 611a fig. 6);
a plurality of dielectric layers (621B and 611B fig. 6, fig. 9A-9D sufficiently embodies a process where 902 substantially identical to 621B and 611B is formed from a least 3 integral layers and/or layering steps); and
a plurality of metal layers (623, 624a, 624b, 613, 614a, 614b fig. 6) in the plurality of dielectric layers; and
one or more ferromagnetic through silicon vias (622a and 612a fig. 6, the TSVs are disclosed as ferro magnetic in “nickel, iron, cobalt, niobium, or an alloy thereof” column 5 lines 50-52) vertically positioned through the individual semiconductor chip [sufficiently illustrated fig. 6].
Claim 8 Kirby teaches as shown above the apparatus of claim 7 includes:
a plurality of inductive links (613 and 624), wherein an individual inductive link of the plurality of inductive links communicates through the individual ferromagnetic through silicon via at one or more frequencies, wherein the individual inductive link is configured to enable wireless transmission of AC power signals or wireless communication between two semiconductor chips of the plurality of semiconductor chips [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed], wherein the individual inductive link comprises:
a first inductive coil (623 fig. 6) in a first metal layer of the plurality of metal layers of a first semiconductor chip of the plurality of semiconductor chips [sufficiently illustrated fig. 6], wherein the first inductive coil surrounds a ferromagnetic through silicon via of the one or more ferromagnetic through silicon vias [sufficiently illustrated fig. 6]; and
a second inductive coil (613 fig. 6) in a second metal layer of the plurality of metal layers of a second semiconductor chip of the plurality of semiconductor chips, wherein the second inductive coil surrounds the individual ferromagnetic through silicon via [sufficiently illustrated fig. 6], wherein the second inductive coil substantially overlaps the first inductive coil [sufficiently illustrated fig. 6], wherein the second inductive coil is magnetically coupled with the first inductive coil at the one or more frequencies [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed].
Claim 9 Kirby teaches as shown above the apparatus of claim 7, wherein a shape of a cross-section of individual ferromagnetic through silicon via comprises one of a rectangular shape, a square shape, a hexagonal shape, an octagonal shape, a circular shape, an elliptical shape, or any combination thereof [sufficiently embodied as elliptical fig. 2 and fig. 8].
Claim 10 Kirby teaches as shown above the apparatus of claim 7 includes:
a plurality of resonant links (623 and 613 fig. 6), wherein an individual resonant link of the plurality of resonant links communicates through a wireless channel of the individual ferromagnetic through silicon via at a resonant frequency, wherein the individual resonant link is configured to enable wireless transmission of AC power signals or wireless communication between two semiconductor chips of the plurality of semiconductor chips [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed], wherein the wireless transmission of the AC power signals protects the wireless channel against electromigration [met under MPEP 2112.01 the structure is the same as disclosed and/or claimed thus the claimed property is presumed], wherein the individual resonant link comprises:
a first inductive coil (623 fig. 6) in a first metal layer of the plurality of metal layers of a first semiconductor chip of the plurality of semiconductor chips [sufficiently illustrated fig. 6], wherein the first inductive coil surrounds the individual ferromagnetic through silicon via [sufficiently illustrated fig. 6];
a first resonating circuit coupled to the first inductive coil, wherein the first resonating circuit and the first inductive coil are configured to communicate at the resonant frequency [sufficiently discloses “operably connected to other circuit elements” column 11 lines 60-65, wherein “other circuit elements (not shown), including one or more rectifiers to revert a coupled alternating current to DC and one or more capacitors or other filter elements to provide steady current” Column 9 lines 40-45 as the embodiment of 400 fig. 4 is substantially similar to the embodiment of 600 fig. 6, in view of this the current starts as DC converted to AC power-coupled and/or transformed through the device of fig. 6 and reverted and/or converted back to DC by the “other circuit elements” operably connected];
a second inductive coil (613 fig. 6) in a second metal layer of the plurality of metal layers of a second semiconductor chip of the plurality of semiconductor chips [sufficiently illustrated fig. 6], wherein the second inductive coil surrounds the individual ferromagnetic through silicon via of the one or more ferromagnetic through silicon vias [sufficiently illustrated fig. 6], wherein the second inductive coil substantially overlaps the first inductive coil [sufficiently illustrated fig. 6], wherein the second inductive coil is magnetically coupled with the first inductive coil [sufficiently illustrated fig. 6 and in view of the above]; and
a second resonating circuit coupled to the second inductive coil [sufficiently discloses “operably connected to other circuit elements” column 11 lines 40-45], wherein the second resonating circuit and the second inductive coil are configured to communicate at the resonant frequency [met under MPEP 2112.01 it is structurally the same and/or identical to what is disclosed and met in view of the above].
Claim 14 Kirby teaches as shown above the apparatus of claim 7, wherein the plurality of semiconductor chips include:
a plurality of inductive links (623 and 612 fig. 6), wherein an individual inductive link of the plurality of inductive links communicates through the individual ferromagnetic through silicon via at one or more frequencies, wherein the individual inductive link is configured to enable wireless communication between two semiconductor chips of the plurality of semiconductor chips, wherein individual inductive link comprises [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed]:
a first flux inducing circuit which is configured to generate a magnetic flux, wherein the first flux inducing circuit surrounds the individual ferromagnetic through silicon via [sufficiently illustrated fig. 6 in view of the above 623 is at least part of a flux inducing circuit];
a second flux inducing circuit which is configured to receive the magnetic flux [sufficiently illustrated fig. 6 in view of the above 613 is at least part of a flux inducing circuit], wherein the second flux inducing circuit surrounds the individual ferromagnetic through silicon via, wherein the second flux inducing circuit substantially overlaps the first flux inducing circuit, wherein the second flux inducing circuit is magnetically coupled with the first flux inducing circuit at the one or more frequencies [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed]; and
wherein the first flux inducing circuit and the second flux inducing circuit comprise one or more of oscillators, transistors, resistors, conductive loops, or any combination thereof [sufficiently illustrated as conductive loops fig. 6, in addition sufficiently disclosed as “other circuit elements (not shown)” column 11 lines 44-45 and lines 61-63].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kirby as applied to the claims above, and further in view of US 10134671 B1 Kirby hereafter “Kirby II”.
Claim 2 Kirby teaches as shown above the apparatus of claim 1, wherein the 3D integrated circuit includes: a ferromagnetic power transformer [as shown above in claim 1].
Kirby does not explicitly teach a plurality of ferromagnetic power transformers.
Kirby II teaches a substantially identical and/or similar 3D integrated circuit including; a plurality of ferromagnetic power transformers [sufficiently illustrated fig. 6 in view of the embodiment of the ferromagnetic power transformer as illustrated fig. 9].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the device of Kirby in view of Kirby II and/or combine the devices such that “the 3D integrated circuit includes; a plurality of ferromagnetic power transformers”.
A person of ordinary skill in the art would have been motivated to make this modification as combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is multi-die semiconductor devices for the purpose of power coupling and/or transforming.
In addition, duplication of parts is prima facie type obviousness [See MPEP 2144.04 VI B.]
In view of the above the following limitations are met necessarily met as there are a plurality of the device of claim 1 “wherein an individual ferromagnetic power transformer of the plurality ferromagnetic power transformers includes:
a plurality of power transmission semiconductor chips, wherein an individual power transmission semiconductor chip of the plurality of power transmission semiconductor chips overlaps with one or more power reception semiconductor chips of the plurality of power reception semiconductor chips, wherein the individual power transmission semiconductor chip wirelessly transmits the AC power signals to the one or more power reception semiconductor chips of the plurality of power reception semiconductor chips via the wireless power transfer channel at the one or more frequencies; and
a plurality of ferromagnetic through silicon vias, wherein an individual ferromagnetic through silicon via of the plurality of ferromagnetic through silicon vias is substantially in a center of a plurality of inductive coils of the power transmission semiconductor chip and the one or more power reception semiconductor chips of the plurality of power reception semiconductor chips, wherein the individual ferromagnetic through silicon via provides a wireless power transfer channel to wirelessly transfer the AC power signals between the power transmission semiconductor chip and the one or more power reception semiconductor chips at the one or more frequencies.”
Claims 11-12, 15-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kirby as applied to the claims above, and further in view of US 20080013350 A1 Golizek et al.
Claim 11 Kirby teaches as shown above the apparatus of claim 7, wherein the 3D integrated circuit includes:
Kirby does not explicitly teach one or more heat dissipation structures configured to dissipate heat away from the 3D integrated circuit during its operation, wherein the one or more heat dissipation structures comprise one or more heat sinks, thermal spreaders, or thermal interface materials, wherein the one or more heat dissipation structures overlap one or more semiconductor chips of the plurality of semiconductor chips, wherein the one or more heat dissipation structures are configured to dissipate heat away from the individual ferromagnetic through silicon via.
Goliszek teaches a step down/step-up isolation transformer, wherein a cooling heat-sink is attached to a flat surface of the planar ferrite core of the transformer [Paragraph 0015 “the use of planar ferrite cores allows cooling heat-sinks to be attached easily to the flat surface of the planar core”].It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kirby in view of Goliszek such that “one or more heat dissipation structures configured to dissipate heat away from the 3D integrated circuit during its operation, wherein the one or more heat dissipation structures comprise one or more heat sinks, thermal spreaders, or thermal interface materials, wherein the one or more heat dissipation structures overlap one or more semiconductor chips of the plurality of semiconductor chips, wherein the one or more heat dissipation structures are configured to dissipate heat away from the individual ferromagnetic through silicon via.”.
A person of ordinary skill in the art would have been motivated to make this modification to enable device operation at high currents and/or to effectively dissipate heat [sufficiently disclosed paragraph 0037 Goliszek “Finally, the planar ferrite core allows the use of cooling heat sinks disposed in heat exchange relationship to the flat surface of the planar core. This aspect can be significant when the transformer 210 is operating at high currents”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. in this case combining known power-couples and/or transformers for the purpose of transforming power and/or transmitting power.
Claim 12 Kirby teaches the apparatus of claim 7, wherein the plurality of semiconductor chips include:
Kirby does not teach one or more heat conductive lines which are configured to form a thermal pathway between the one or more semiconductor chips of the plurality of semiconductor chips and the one or more ferromagnetic through silicon vias to facilitate dissipation of heat generated by the individual semiconductor chip.
Goliszek teaches a step down/step-up isolation transformer, wherein a cooling heat-sink is attached to a flat surface of the planar ferrite core of the transformer [Paragraph 0015 “the use of planar ferrite cores allows cooling heat-sinks to be attached easily to the flat surface of the planar core”].It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kirby in view of Goliszek such that one or more heat conductive lines which are configured to form a thermal pathway between the one or more semiconductor chips of the plurality of semiconductor chips and the one or more ferromagnetic through silicon vias to facilitate dissipation of heat generated by the individual semiconductor chip.
A person of ordinary skill in the art would have been motivated to make this modification to enable device operation at high currents and/or to effectively dissipate heat [sufficiently disclosed paragraph 0037 Goliszek “Finally, the planar ferrite core allows the use of cooling heat sinks disposed in heat exchange relationship to the flat surface of the planar core. This aspect can be significant when the transformer 210 is operating at high currents”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. in this case combining known power-couples and/or transformers for the purpose of transforming power and/or transmitting power
Claim 15 Kirby teaches an apparatus of a ferromagnetic transformer in a 3D integrated circuit, the apparatus comprising:
a plurality of semiconductor chips (610 and 620 fig. 6) stacked within the 3D integrated circuit, wherein one or more semiconductor chips of the plurality of semiconductor chips are configured to generate heat [met under MPEP 2112.01 the structure is the same and disclosed thus the function and/or property of generating heat is presumed]; and
one or more ferromagnetic through silicon vias (621a and 622b) vertically positioned through the one or more semiconductor chips, wherein an individual ferromagnetic through silicon via of one or more ferromagnetic through silicon vias is configured to behave as a heat pipe that conducts heat from the one or more semiconductor chips [met under MPEP 2112.01]
Kirby does not teach that the heat pipes conduct heat to an ambient heat sink.
Goliszek teaches a step down/step-up isolation transformer, wherein a cooling heat-sink is attached to a flat surface of the planar ferrite core of the transformer [Paragraph 0015 “the use of planar ferrite cores allows cooling heat-sinks to be attached easily to the flat surface of the planar core”].It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kirby in view of Goliszek such that the heat pipes conduct heat to an ambient heat sink.
A person of ordinary skill in the art would have been motivated to make this modification to enable device operation at high currents and/or to effectively dissipate heat [sufficiently disclosed paragraph 0037 Goliszek “Finally, the planar ferrite core allows the use of cooling heat sinks disposed in heat exchange relationship to the flat surface of the planar core. This aspect can be significant when the transformer 210 is operating at high currents”].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. in this case combining known power-couples and/or transformers for the purpose of transforming power and/or transmitting power.
Claim 16 Kirby in view of Goliszek teaches as shown above the apparatus of claim 15 includes:
a plurality of two or more overlapping inductive coils (613 and 623 fig. 6), wherein two or more overlapping inductive coils of the plurality of two or more overlapping inductive coils surround the individual ferromagnetic through silicon via [sufficiently illustrated fig. 6], wherein the two or more overlapping inductive coils are magnetically coupled through the individual ferromagnetic through silicon via to enable wireless transmission of AC power signals or wireless communication between two or more semiconductor chips of the plurality of semiconductor chips [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed].
Claim 17 Kirby in view of Goliszek teaches as shown above the apparatus of claim 15 includes:
one or more pairs of overlapping inductive coils (613 and 623 fig. 6), wherein an individual pair of overlapping inductive coils of the one or more pairs of overlapping inductive coils surround the individual ferromagnetic through silicon via [sufficiently illustrated fig. 6], wherein the individual pair of overlapping inductive coils is magnetically coupled through the individual ferromagnetic through silicon via to enable wireless transmission of AC power signals or wireless communication between two or more semiconductor chips of the plurality of semiconductor chips [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed].
Claim 18 Kirby in view of Goliszek teaches as shown above the apparatus of claim 15, wherein a shape of a cross-section of the individual ferromagnetic through silicon via comprises one of a rectangular shape, a square shape, a hexagonal shape, an octagonal shape, a circular shape, or an elliptical shape [sufficiently illustrated/embodied as elliptical fig. 2 and 8].
Claim 20 Kirby in view of Goliszek teaches as shown above the apparatus of claim 15, wherein the plurality of semiconductor chips includes:
a plurality of inductive links (613 and 623 fig. 6), wherein an individual inductive link of the plurality of inductive links communicates through the individual ferromagnetic through silicon via of the one or more ferromagnetic through silicon vias at one or more frequencies, wherein the individual inductive link is configured to enable wireless transmission of AC power signals or wireless communication between two semiconductor chips of the plurality of semiconductor chips [Disclosed with sufficient specificity column 12 lines 19-34 “By changing the current passing through the second conductor 623…a changing magnetic field can be induced in the four TSVs 612a, 612b, 622a and 622b…which in turn induces a changing current in the first conductor 613. In this fashion, signals and/or power can be coupled between a circuit comprising the second conductor 623 and another comprising the first conductor 613” and/or met under MPEP 2112.01 the structure is structurally and/or materially the same and/or identical to what is disclosed and/or claimed].
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kirby as applied to the claims above, and in further view of US 20090027243 A1 Leung et al hereafter “Leung”
Claim 13 Kirby teaches he apparatus of claim 7,
Kirby does not explicitly teach the plurality of semiconductor chips include one or more of: central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chip (SoC) architectures, digital signal processors (DSPs), microcontroller units (MCUs), artificial intelligence (AI) accelerators, neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), inference processing units (IPUs), vision processing units (VPUs), coprocessors, cryptographic accelerators, memory controllers, power management integrated circuits (PMICs), display controllers, audio processors, sensor hubs, or any combination thereof.
Leung teaches using transformers to isolate voltage between adjacent semiconductor chips (fig. 12), explicitly between adjacent MCUs [Paragraph 0063 “The transformer 1214 electromagnetically couples the RF carrier signal to transformer 1218 via lines 1216. This links the data represented by the RF carrier signal between the first MCU and the second MCU while providing voltage isolation between the MCUs via the first and second transformers 1214, 1218. Each of the transformers 1214 and 1218 are associated with a particular MCU on opposite sides of interface 122”]
It would have been obvious to one of ordinary skill in the art to provide the device of Kirby in combination semiconductor chips including “include one or more of: central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chip (SoC) architectures, digital signal processors (DSPs), microcontroller units (MCUs), artificial intelligence (AI) accelerators, neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), inference processing units (IPUs), vision processing units (VPUs), coprocessors, cryptographic accelerators, memory controllers, power management integrated circuits (PMICs), display controllers, audio processors, sensor hubs, or any combination thereof” to provide important discrete element circuits to the semiconductor chips, such as impedance-matching circuits, linear filters and various power circuits with the benefit of miniaturization [column 1 lines 50-55 Kirby] and/or to provide an isolation link between two separate chips [Paragraph 0063 Leung].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is multi-die/chip semiconductor devices for the purpose of forming a multi-die/chip semiconductor device.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kirby in view of Goliszek as applied to the claims above, and in further view Leung.
Claim 19 Kirby in view of Goliszek teaches as shown above the apparatus of claim 15,
Kirby does not explicitly teach wherein the plurality of semiconductor chips include one or more of: central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chip (SoC) architectures, digital signal processors (DSPs), microcontroller units (MCUs), artificial intelligence (AI) accelerators, neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), inference processing units (IPUs), vision processing units (VPUs), coprocessors, cryptographic accelerators, memory controllers, power management integrated circuits (PMICs), display controllers, audio processors, sensor hubs, or any combination thereof.
Leung teaches using transformers to isolate voltage between adjacent semiconductor chips (fig. 12), explicitly between adjacent MCUs [Paragraph 0063 “The transformer 1214 electromagnetically couples the RF carrier signal to transformer 1218 via lines 1216. This links the data represented by the RF carrier signal between the first MCU and the second MCU while providing voltage isolation between the MCUs via the first and second transformers 1214, 1218. Each of the transformers 1214 and 1218 are associated with a particular MCU on opposite sides of interface 122”]
It would have been obvious to one of ordinary skill in the art to provide the device of Kirby in combination semiconductor chips including “include one or more of: central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chip (SoC) architectures, digital signal processors (DSPs), microcontroller units (MCUs), artificial intelligence (AI) accelerators, neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), inference processing units (IPUs), vision processing units (VPUs), coprocessors, cryptographic accelerators, memory controllers, power management integrated circuits (PMICs), display controllers, audio processors, sensor hubs, or any combination thereof” to provide important discrete element circuits to the semiconductor chips, such as impedance-matching circuits, linear filters and various power circuits with the benefit of miniaturization [column 1 lines 50-55 Kirby] and/or to provide an isolation link between two separate chips [Leung Paragraph 0063].
In addition, combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is multi-die/chip semiconductor devices for the purpose of forming a multi-die/chip semiconductor device.
Conclusion
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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