Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (Pub. No. US 20130146936), hereinafter referred to as Tsai, in view of Lee et al. (Pub. No. US 20240079272 A1), hereinafter referred to as Lee.
Regarding claim 1, Tsai teaches a light-emitting diode (LED), comprising: a substrate, having a upper surface and a lower surface disposed opposite to the upper surface (Fig. 3, emitting diode structure 10, substrate 12; ¶105); an epitaxial layer, disposed on the upper surface of the substrate, wherein the epitaxial layer comprises: a first semiconductor layer, an active layer, and a second semiconductor layer which are sequentially stacked in that order (Fig. 3, first semiconductor layer 12, light emitting layer 16, second semiconductor layer 18; ¶105); and a protective layer, covering the epitaxial layer (Figs. 10 and 11A, passivation layer 24; ¶107); wherein the epitaxial layer is divided into a plurality of chiplets, each chiplet comprises: sidewalls intersecting in transverse and longitudinal directions, and the sidewalls of each chiplet comprise: transverse sidewalls and longitudinal sidewalls (Figs. 21A&B and 27, scribe line 50, LED chip 100, boundary 80; ¶116-118); every adjacent two of the plurality of chiplets define a dicing channel, and the dicing channels of the plurality of chiplets comprise transverse dicing channels and longitudinal dicing channels extending respectively in the transverse and longitudinal directions (Figs. 21A&B, scribe line 50; ¶116); and the protective layer covers the dicing channels of the plurality of chiplets and the sidewalls of the plurality of chiplets (Figs. 10 and 11A, passivation layer 24; ¶107). However, Tsai does not explicitly teach the protective layer is provided with a patterned structure in each intersecting area of the transverse dicing channels and the longitudinal dicing channels, and the patterned structure comprises a groove extending toward the substrate.
Lee teaches the protective layer is provided with a patterned structure in each intersecting area of the transverse dicing channels and the longitudinal dicing channels, and the patterned structure comprises a groove extending toward the substrate (Figs. 1, 2, 6, and 7, scribe lane region 120, organic layer 400, dicing grooves 350; ¶20-30, 36-43).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that the protective layer is provided with a patterned structure in each intersecting area of the transverse dicing channels and the longitudinal dicing channels, and the patterned structure comprises a groove extending toward the substrate. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
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Regarding claim 2, Tsai does not explicitly teach the patterned structure comprises a cross-shaped structure intersecting in the transverse and longitudinal directions, and each branch of the cross-shaped structure extends to a corresponding one of the dicing channels of the plurality of chiplets.
Lee teaches the patterned structure comprises a cross-shaped structure intersecting in the transverse and longitudinal directions, and each branch of the cross-shaped structure extends to a corresponding one of the dicing channels of the plurality of chiplets (Fig. 6, dicing grooves 350, branches 350B, first dicing line DLX, second dicing line DLY; ¶36-48).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that the patterned structure comprises a cross-shaped structure intersecting in the transverse and longitudinal directions, and each branch of the cross-shaped structure extends to a corresponding one of the dicing channels of the plurality of chiplets. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
Regarding claim 3, Tsai does not explicitly teach each branch of the cross-shaped structure has a length in an extension direction and a width in a direction intersecting the extension direction, an extension length of each branch outside an overlapping area of the dicing channels is greater than or equal to 0.1 μm, and less than or equal to 1/2 of a length of a sidewall of a corresponding one of the plurality of chiplets in a length direction.
Lee teaches each branch of the cross-shaped structure has a length in an extension direction and a width in a direction intersecting the extension direction, an extension length of each branch outside an overlapping area of the dicing channels is greater than or equal to 0.1 μm, and less than or equal to 1/2 of a length of a sidewall of a corresponding one of the plurality of chiplets in a length direction (Fig. 10, dicing groove 350, modified patterns 210; ¶49).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that each branch of the cross-shaped structure has a length in an extension direction and a width in a direction intersecting the extension direction, an extension length of each branch outside an overlapping area of the dicing channels is greater than or equal to 0.1 μm, and less than or equal to 1/2 of a length of a sidewall of a corresponding one of the plurality of chiplets in a length direction. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
Regarding claim 4, Tsai teaches a dicing channel width of 10 nm to 1 mm (Figs. 21A&B, scribe line 50; ¶116). However, Tsai does not explicitly teach the width of each branch is greater than or equal to 0.1 μm, and less than or equal to 2/3 of a width of the corresponding dicing channel.
Lee teaches the width of each branch is greater than or equal to 0.1 μm (Fig. 10, dicing groove 350, modified patterns 210; ¶49). Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that the width of each branch is greater than or equal to 0.1 μm, and less than or equal to 2/3 of a width of the corresponding dicing channel. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
Regarding claim 5, Tsai does not explicitly teach in an extension direction of each branch of the cross-shaped structure, a distance between each branch of the cross-shaped structure and a sidewall of a corresponding one of the plurality of chiplets is greater than or equal to 0.1 μm, and less than or equal to 1/2 of a width of the corresponding dicing channel; and four branches of the cross-shaped structure have a same length or different lengths.
Lee teaches in an extension direction of each branch of the cross-shaped structure, a distance between each branch of the cross-shaped structure and a sidewall of a corresponding one of the plurality of chiplets is greater than or equal to 0.1 μm, and less than or equal to 1/2 of a width of the corresponding dicing channel; and four branches of the cross-shaped structure have a same length or different lengths (Fig. 10, dicing groove 350, modified patterns 210; ¶49).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that in an extension direction of each branch of the cross-shaped structure, a distance between each branch of the cross-shaped structure and a sidewall of a corresponding one of the plurality of chiplets is greater than or equal to 0.1 μm, and less than or equal to 1/2 of a width of the corresponding dicing channel; and four branches of the cross-shaped structure have a same length or different lengths. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
Regarding claim 6, Tsai does not explicitly teach the groove extending into the protective layer along a depth direction, and at most penetrates through the protective layer.
Lee teaches the groove extending into the protective layer along a depth direction, and at most penetrates through the protective layer (Fig. 7, dicing groove 350, organic layer 400; ¶39-53).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that the groove extends into the protective layer along a depth direction, and at most penetrates through the protective layer. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
Regarding claim 7, Tsai does not explicitly teach the groove extending through the protective layer along a depth direction and extends to below an upper surface of the epitaxial layer.
Lee teaches the groove extends through the protective layer along a depth direction, and extends to below an upper surface of the epitaxial layer (Fig. 7, dicing groove 350, organic layer 400, active layer 300; ¶39-53).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that the groove extends through the protective layer along a depth direction, and extends to below an upper surface of the epitaxial layer. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
Regarding claim 9, Tsai does not explicitly teach a depth of the groove is greater than or equal to 0.01 μm; and a ratio of the depth of the groove to a thickness of the protective layer is greater than or equal to 1:3.
Lee teaches a depth of the groove is greater than or equal to 0.01 μm; and a ratio of the depth of the groove to a thickness of the protective layer is greater than or equal to 1:3 (Fig. 7, dicing groove 350, organic layer 400, active layer 300; ¶39-53).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that a depth of the groove is greater than or equal to 0.01 μm; and a ratio of the depth of the groove to a thickness of the protective layer is greater than or equal to 1:3. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
Regarding claim 19, Tsai further teaches a LED chiplet, obtained by dicing the LED as claimed in claim 1 (Figs. 21A&B, 27A, LED chip 100; ¶118).
Regarding claim 20, Tsai further teaches a light-emitting device, comprising: a substrate and a light-emitting element fixed on the substrate; wherein the light-emitting element comprises at least one LED chiplet as claimed in claim 19 (Figs. 41, 42, 45, 46, LED chip 100, submount 110, light emitting diode package structure 200; ¶118-121).
Claim(s) 8, 10, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Lee as applied to claims 1 and 2 above, and further in view of Matsuura et al. (Pub. No. US 20030216009 A1), hereinafter referred to as Matsuura.
Regarding claim 8, Tsai does not explicitly teach the groove extending through the protective layer and the epitaxial layer along a depth direction, and extends to the upper surface of the substrate.
Lee teaches the groove extends through the protective layer and the epitaxial layer along a depth direction (Fig. 7, dicing groove 350, organic layer 400, active layer 300; ¶39-53).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that the groove extends through the protective layer and the epitaxial layer along a depth direction. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
However, Tsai in view of Lee does not teach the groove extending to the upper surface of the substrate.
Matsuura teaches the groove extending through the epitaxial layer to the upper surface of the substrate (Fig. 4, groove 11, epitaxial layer 1b, semiconductor wafer 1a; ¶86).
Tsai, Lee, and Matsuura are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee with the teachings of Matsuura such that the groove extends through the epitaxial layer to the upper surface of the substrate. For the purpose of improving dicing of semiconductor chips and to attenuate stress in the device, as recognized by Matsuura.
Regarding claim 10, Tsai does not explicitly teach the cross-shaped structure forms a cross-shaped island, and the cross-shaped island comprises: a cross-shaped groove located at the intersecting area of the dicing channels, and a cross-shaped island body located inside the cross-shaped groove; wherein an edge of the cross-shaped island body and an edge of the cross-shaped groove define a gap.
Lee teaches the cross-shaped structure forming a cross-shaped groove located at the intersecting area of the dicing channels (Fig. 6, dicing grooves 350, branches 350B, first dicing line DLX, second dicing line DLY; ¶36-48).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that the cross-shaped structure forms a cross-shaped groove located at the intersecting area of the dicing channels. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
However, Tsai in view of Lee does not explicitly teach the cross-shaped structure forming a cross-shaped island body located inside the cross-shaped groove; wherein an edge of the cross-shaped island body and an edge of the cross-shaped groove define a gap.
Matsuura teaches the cross-shaped structure forming a cross-shaped island body located inside a groove; wherein an edge of the cross-shaped island body and an edge groove define a gap (Figs. 7 and 12, alignment pattern forming region 23, groove 11, alignment pattern 25a; ¶97-109).
Tsai, Lee, and Matsuura are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee with the teachings of Matsuura such that the cross-shaped structure forms a cross-shaped island, and the cross-shaped island comprises: a cross-shaped groove located at the intersecting area of the dicing channels, and a cross-shaped island body located inside the cross-shaped groove; wherein an edge of the cross-shaped island body and an edge of the cross-shaped groove define a gap. For the purpose of improving dicing of semiconductor chips, attenuating stress in the device, increasing yield of the semiconductor devices, lower manufacturing costs, and the ability to use the cross-shaped structure as an alignment pattern, as recognized by Matsuura.
Regarding claim 11, Tsai teaches the protective layer located in the dicing channel (Figs. 10 and 11A, passivation layer 24; ¶107). However, Tsai does not explicitly teach an upper surface of a part of the protective layer located at the cross-shaped island and an upper surface of a part of the protective layer located at the dicing channels are at a same height.
Matsuura teaches an upper surface of the cross-shaped island and an upper surface of the non-groove regions located at the dicing channels are at a same height (Fig. 9, alignment pattern forming region 23, groove 11, non-groove regions 24; ¶96-103).
Tsai, Lee, and Matsuura are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the protective layer and dicing channel of Tsai with the teachings of Matsuura such that an upper surface of a part of the protective layer located at the cross-shaped island and an upper surface of a part of the protective layer located at the dicing channels are at a same height. For the purpose of improving dicing of semiconductor chips, attenuating stress in the device, increasing yield of the semiconductor devices, lower manufacturing costs, and the ability to use the cross-shaped structure as an alignment pattern, as recognized by Matsuura.
Regarding claim 18, Tsai in view of Lee does not explicitly teach the patterned structure is configured as a dicing mark capable of being identified by dicing equipment.
Matsuura teaches the patterned structure is configured as a dicing mark capable of being identified by dicing equipment (Alignment pattern forming regions 23, alignment patterns 25a-25d; ¶101-109).
Tsai, Lee, and Matsuura are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee with the teachings of Matsuura such that the patterned structure is configured as a dicing mark capable of being identified by dicing equipment. For the purpose of improving dicing of semiconductor chips, attenuating stress in the device, increasing yield of the semiconductor devices, lower manufacturing costs, and the ability to use the patterned structure as an alignment pattern, as recognized by Matsuura.
Claim(s) 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Lee as applied to claim 1 above, and further in view of Park et al. (Pub. No. US 20220216162 A1), hereinafter referred to as Park, and Chen et al. (US Patent No. 7,211,500), hereinafter referred to as Chen.
Regarding claim 12, Tsai in view of Lee does not explicitly teach the patterned structure is an array structure, and the array structure comprises: a central notch located at the intersecting area, and a plurality of strip grooves arranged in an array along extension directions of the dicing channels from the central notch; wherein an extension direction of each strip groove is perpendicular to the extension direction of one of the dicing channels where the strip groove is located.
Chen teaches a central notch located at the intersecting area (Fig. 2B, recess pattern 102; Col. 3, line 57 – Col 4, line 53).
Tsai, Lee, and Chen are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee with the teachings of Chen such that there is a central notch located at the intersecting area. For the purpose of improving dicing of semiconductor chips by reducing the damage caused by the dicing process, as recognized by Chen.
However, Tsai in view of Lee and further in view of Chen does not explicitly teach a plurality of strip grooves arranged in an array along extension directions of the dicing channels from the central notch; wherein an extension direction of each strip groove is perpendicular to the extension direction of one of the dicing channels where the strip groove is located.
Park teaches a plurality of strip grooves arranged in an array along extension directions of the dicing channels from the central notch; wherein an extension direction of each strip groove is perpendicular to the extension direction of one of the dicing channels where the strip groove is located (Fig. 2B, open area 10, notch patterns 10N, key patterns 20; ¶29).
Tsai, Lee, Chen, and Park are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee and Chen with the teachings of Park such that the patterned structure is an array structure, and the array structure comprises: a central notch located at the intersecting area, and a plurality of strip grooves arranged in an array along extension directions of the dicing channels from the central notch; wherein an extension direction of each strip groove is perpendicular to the extension direction of one of the dicing channels where the strip groove is located. For the purpose of improving dicing of semiconductor chips and using the array structure as a key pattern for alignment, as recognized by Park.
Regarding claim 13, Tsai teaches the width of the scribe lines between 10 nm and 1 mm (¶116). However, Tsai does not explicitly teach the width of each strip groove is greater than or equal to 0.1 μm.
Park teaches the strip grooves are formed in the scribe line regions (Fig. 2B, scribe line regions 110, open areas 10, key patterns 20; ¶21-23, 29).
Tsai, Lee, Chen, and Park are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to size the strip grooves of Park such that they fit in the scribe lines of Tsai such that the width of each strip groove is greater than or equal to 0.1 μm. For the purpose of improving dicing of semiconductor chips and ensuring the strip grooves fit within the scribe lines and can function as key patterns for alignment, as recognized by Park.
Regarding claim 14, Tsai teaches the width of the scribe lines between 10 nm and 1 mm (¶116). However, Tsai does not explicitly teach a ratio of the width of each strip groove to a distance between the strip groove and an adjacent strip groove of the plurality of strip groove is in a range of 1:6 to 5:1, and the adjacent strip groove is one of the plurality of strip grooves facing away from the central notch.
Park teaches the strip grooves are formed in the scribe line regions (Fig. 2B, scribe line regions 110, open areas 10, key patterns 20; ¶21-23, 29) and that the strip grooves may be spaced apart at a constant distant (Figs. 2B and 2D, open areas 10, key patterns 20; ¶29)
Tsai, Lee, Chen, and Park are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to size the strip grooves of Park such that they fit in the scribe lines of Tsai such that a ratio of the width of each strip groove to a distance between the strip groove and an adjacent strip groove of the plurality of strip groove is in a range of 1:6 to 5:1, and the adjacent strip groove is one of the plurality of strip grooves facing away from the central notch. For the purpose of improving dicing of semiconductor chips and ensuring the strip grooves fit within the scribe lines and can function as key patterns for alignment, as recognized by Park.
Regarding claim 15, Tsai does not explicitly teach an arrangement of the plurality of strip grooves is an equidistant array or a non-equidistant array.
Park teaches an arrangement of the plurality of strip grooves is an equidistant array or a non-equidistant array (Figs. 2B and 2D, open areas 10, key patterns 20; ¶29).
Tsai, Lee, Chen, and Park are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee and Chen with the teachings of Park such that the plurality of strip grooves is an equidistant array or a non-equidistant array. For the purpose of improving dicing of semiconductor chips and ensuring the strip grooves fit within the scribe lines and can function as key patterns for alignment, as recognized by Park.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Lee as applied to claim 1 above, and further in view of Lee et al. (Patent No. US 7,952,167), hereinafter referred to as Lee (2011).
Regarding claim 16, Tsai does not explicitly teach the patterned structure is an array structure, and the array structure comprises: a cross-shaped slot located at the intersecting area; wherein the cross-shaped slot comprise: a transverse branch and a longitudinal branch extending respectively in the transverse and longitudinal directions; and a plurality of linear slots, comprising: transverse linear slots and longitudinal linear slots; wherein the transverse linear slots are distributed within the dicing channels with the transverse branch of the cross-shaped slot as a symmetry axis, and the longitudinal linear slots are distributed within the dicing channels with the longitudinal branch of the cross-shaped slot as a symmetry axis.
Lee teaches a cross-shaped slot located at the intersecting area; wherein the cross-shaped slot comprise: a transverse branch and a longitudinal branch extending respectively in the transverse and longitudinal directions (Fig. 6, dicing grooves 350, branches 350B, first dicing line DLX, second dicing line DLY; ¶36-48).
Tsai and Lee are analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai with the teachings of Lee such that a cross-shaped slot is located at the intersecting area; wherein the cross-shaped slot comprises a transverse branch and a longitudinal branch extending respectively in the transverse and longitudinal directions. For the purpose of improving dicing of semiconductor chips such as by preventing layer delamination, as recognized by Lee.
However, Tsai in view of Lee does not explicitly teach a plurality of linear slots, comprising: transverse linear slots and longitudinal linear slots; wherein the transverse linear slots are distributed within the dicing channels with the transverse branch of the cross-shaped slot as a symmetry axis, and the longitudinal linear slots are distributed within the dicing channels with the longitudinal branch of the cross-shaped slot as a symmetry axis.
Lee (2011) teaches a plurality of linear slots, comprising: transverse linear slots and longitudinal linear slots; wherein the transverse linear slots are distributed within the dicing channels with the transverse branch of the cross-shaped slot as a symmetry axis, and the longitudinal linear slots are distributed within the dicing channels with the longitudinal branch of the cross-shaped slot as a symmetry axis (Figs. 5 and 6, scribe line 103, grooves 501, grooves 601; Col. 5, lines 9 - 62).
Tsai, Lee, and Lee (2011) are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee with the teachings of Lee (2011) such that the patterned structure is an array structure, and the array structure comprises: a cross-shaped slot located at the intersecting area; wherein the cross-shaped slot comprise: a transverse branch and a longitudinal branch extending respectively in the transverse and longitudinal directions; and a plurality of linear slots, comprising: transverse linear slots and longitudinal linear slots; wherein the transverse linear slots are distributed within the dicing channels with the transverse branch of the cross-shaped slot as a symmetry axis, and the longitudinal linear slots are distributed within the dicing channels with the longitudinal branch of the cross-shaped slot as a symmetry axis. For the purpose of improving dicing of semiconductor chips by reducing the damage caused by the dicing process, as recognized by Lee (2011).
Regarding claim 17, Tsai in view of Lee does not explicitly teach the linear slots in two of the dicing channels respectively adjacent to the transverse sidewall and the longitudinal sidewall of a corresponding one of the plurality of chiplets are connected to define a L-shaped slot.
Lee (2011) teaches the linear slots in two of the dicing channels respectively adjacent to the transverse sidewall and the longitudinal sidewall of a corresponding one of the plurality of chiplets are connected to define a L-shaped slot (Figs. 5 and 6, scribe line 103, grooves 501, grooves 601; Col. 5, lines 9 - 62).
Tsai, Lee, and Lee (2011) are all analogous art as they are in the same field of endeavor of semiconductor devices and manufacturing. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Tsai in view of Lee with the teachings of Lee (2011) such that the linear slots in two of the dicing channels respectively adjacent to the transverse sidewall and the longitudinal sidewall of a corresponding one of the plurality of chiplets are connected to define a L-shaped slot. For the purpose of improving dicing of semiconductor chips by reducing the damage caused by the dicing process, as recognized by Lee (2011).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang et al. (Pub. No. US 20220262743 A1), Abe et al. (US Patent No. 7,737,001), Kang (Pub. No. US 20240021477 A1), and Pu et al. (US Patent No. 7,888,236).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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