Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “an insulating layer” of independent Claims 1 and 21 must be shown and labeled or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Dependent Claim 6 recites the limitation “the conductive lines and the bonding fingers are disposed at the first height level”. However Claim 1 recites “the conductive layer and the portion of the insulating layer are disposed at a first height level” and “wherein the portion of the insulating layer overlaps the bonding fingers in a vertical direction, and the conductive layer overlaps at least a portion of the conductive lines in the vertical direction”. Therefore, those limitations of Claim 6 are opposite to those limitations of Claim 1.
For purposes of compact prosecution, that Claim 6 limitation will be interpreted to instead recite “the conductive lines and the bonding fingers are not disposed at the first height level”.
Also for purposes of compact prosecution, “in a plane view” at the end of Claim 6 will be interpreted to instead recite “in a plan view”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 12-14, 17-18, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toyama et al. (“Toyama”), US 2015/0237731.
Regarding Claim 1, Toyama discloses a semiconductor package (ED1; Fig. 4; ¶ 0040) comprising:
a substrate (3; Fig. 4; ¶ 0043 “substrate 3”) including conductive lines (3w1; Figs. 4-5A; ¶ 0046), bonding fingers (3p1; Figs. 4-5A; ¶ 0044 “bonding fingers 3p1 includes a power supply bonding finger 3p1(p), a ground bonding finger 3p1(g), and a signal bonding finger 3p1(s)”), and a wiring circuit region (3gp, 3dp; Fig. 4; ¶ 0047-0048), wherein the wiring circuit region is disposed lower than the bonding fingers (Fig. 4);
bonding wires (BW; Fig. 4; ¶ 0056 “bonding wires BW”); and
a first semiconductor chip (2; Fig. 4; ¶ 0041-0042 “semiconductor chip 2”) on the substrate (Fig. 4; ¶ 0056 “semiconductor chip 2 mounted on the upper surface 3a of the wiring substrate 3”), wherein the first semiconductor chip includes pads (2pd; Figs. 3-4; ¶ 0042 “pads (electrodes or electrode pads) 2pd formed on the surface 2a side of the semiconductor chip 2”) disposed on (Figs. 3-4; ¶ 0042 “pads (electrodes or electrode pads) 2pd formed on the surface 2a side of the semiconductor chip 2”) an upper surface thereof (2a; Fig. 3; ¶ 0042 “semiconductor chip 2 has a surface (principal surface or upper surface) 2a”), and each of the pads is electrically connected to a first end of a corresponding one of the bonding wires (Fig. 4; ¶ 0044 “pad 2pd are electrically connected by a bonding wire BW”),
wherein the wiring circuit region includes a conductive layer (3dp; Figs. 4, 6; ¶ 0048 “a copper film, and constitutes a power supply plane 3dp”) and at least a portion of an insulating layer (Fig. 6A unlabeled white portions of the layer containing 3dp located above and below conductive layer 3dp in the Y direction), the conductive layer and the portion of the insulating layer are disposed at a first height level (Fig. 4; ¶ 0048 “third-layer wiring layer is formed of a copper film, and constitutes a power supply plane 3dp”), and the conductive layer and the portion of the insulating layer are coplanar with each other (Figs. 4, 6A; ¶ 0048 ” third-layer wiring layer” and “power supply plane 3dp is an island-like pattern when the wiring substrate 3 is assumed to be the sea”),
wherein each of second ends of the bonding wires is electrically connected to a corresponding one of the bonding fingers (Fig. 4; ¶ 0046 “bonding wire BW is electrically connected with the bonding finger 3p1”), and
wherein the portion of the insulating layer overlaps the bonding fingers in a vertical direction (Figs. 1, 6A in this instance the portion of the insulating layer of Fig. 6A overlaps the top and bottom rows of bonding fingers 3p1 of Fig. 1), and the conductive layer (3dp) overlaps at least a portion of the conductive lines (3w1) in the vertical direction (Fig. 4).
Regarding Claim 2, Toyama discloses wherein the portion of the insulating layer overlaps, in the vertical direction, a region between the bonding fingers (Figs. 1, 6A in this instance the portion of the insulating layer of Fig. 6A overlaps a region between the bonding fingers of the top and bottom rows of bonding fingers 3p1 of Fig. 1).
Regarding Claim 3, Toyama discloses wherein the bonding fingers (3p1) include:
a signal bonding finger (3p1(s)); Fig. 4; ¶ 0044 “signal bonding finger 3p1(s)”) through which a signal is transmitted or received by the first semiconductor chip (Fig. 4; ¶ 0044 “the signal bonding finger 3p1(s) is electrically connected with the signal pad 2pd(s) via a bonding wire BW”; this language is being interpreted to mean that the structure is configured such that a signal would be transmitted or received, furthermore this is how that language is being interpreted throughout the rest of the claims); and
a power bonding finger (3p1(p)); Fig. 4; “power supply bonding finger 3p1(p)”) through which power is supplied to the first semiconductor chip (Fig. 4; ¶ 0044 “the power supply bonding finger 3p1(p) is electrically connected with the power supply pad 2pd(p) via a bonding wire BW”),
wherein the portion of the insulating layer overlaps, in the vertical direction, a region between the signal bonding finger and the power bonding finger (Figs 1 and 6A in this instance the portion of the insulating layer of Fig. 6A overlaps a region between the signal bonding finger and the power bonding finger of the top and bottom rows of bonding fingers 3p1 of Fig. 1; ¶ 0044 “bonding fingers 3p1 are disposed around the semiconductor chip 2 along the four sides of the semiconductor chip 2”).
Regarding Claim 4, Toyama discloses
wherein the signal bonding finger is one of a plurality of signal bonding fingers (Fig. 1 multiple bonding fingers are labeled 3p1(s); ¶ 0044 “shown in FIG. 1, the bonding fingers 3p1 are disposed around the semiconductor chip 2 along the four sides of the semiconductor chip 2”), and
the portion of the insulating layer entirely overlaps, in the vertical direction, a region between the plurality of signal bonding fingers (Figs 1 and 6A in this instance the portion of the insulating layer of Fig. 6A overlaps a region between the plurality of signal bonding fingers of the top and bottom rows of bonding fingers 3p1 of Fig. 1; ¶ 0044 “bonding fingers 3p1 are disposed around the semiconductor chip 2 along the four sides of the semiconductor chip 2”).
Regarding Claim 5, Toyama discloses
wherein the bonding fingers (3p1) include signal bonding fingers (3p1(s); Fig. 4; ¶ 0044 “bonding fingers 3p1 includes…signal bonding finger 3p1(s)”) through which signals are transmitted or received by the first semiconductor chip (Fig. 4; ¶ 0044 “signal bonding finger 3p1(s) is electrically connected with the signal pad 2pd(s) via a bonding wire BW”), and
wherein the signal bonding fingers are configured to transfer signals having a data transmission rate of 10 Gbps or more (Fig. 4; ¶ 0044 the signal bonding fingers can transfer signals having a data transmission rate of 10 Gbps or more).
Regarding Claim 6, Toyama discloses wherein:
each of the conductive lines is electrically connected to a corresponding one of the bonding fingers (Figs. 4, 5A; ¶ 0046 “3w1 and the bonding finger 3p1 are formed as one body”),
the conductive lines and the bonding fingers are disposed at the first height level (Fig. 4; ¶ 0046 “first-layer wiring layer is formed of a copper film and constitutes the bonding fingers 3p1 and a plurality of wirings 3w1”),
the conductive lines and the bonding fingers are coplanar with each other (Fig. 4; ¶ 0046 “first-layer wiring layer is formed of a copper film and constitutes the bonding fingers 3p1 and a plurality of wirings 3w1”),
the conductive layer (3dp) includes a through-hole (Fig. 6A in this instance a through-hole containing the insulating layer),
the through-hole entirely overlaps, in the vertical direction, a region between the bonding fingers (Figs. 1 and 6A in this instance the lower through-hole of Fig. 6A overlaps in the vertical direction a region between the bonding fingers 3p1 of the bottom row of bonding fingers of Fig. 1), and
an area of the through-hole (Fig. 6A in this instance a middle section of the bottom through-hole that overlaps a region between the bonding fingers) is smaller than an area of the conductive layer (Fig. 6A the area of 3dp) in a plane view (Fig. 6A in this instance an area of that middle section of the bottom through-hole is smaller than an area of conductive layer 3dp in a plan view).
Regarding Claim 12, Toyama discloses wherein the substrate further includes:
external connection terminals (3p2(p); Fig. 4; ¶ 0054 “power supply land 3p2(p)”) disposed to be lower than the conductive layer (Fig. 4); and
external connection lines (3v; Fig. 4 in this instance the two external connection lines on the right side; ¶ 0054 “conductor layer 3v”) electrically connected to the external connection terminals (Fig. 4; ¶ 0054 ” power supply bonding finger 3p1(p) is electrically connected with the power supply plane 3dp via the via conductor layer 3v and further electrically connected with the power supply land 3p2(p) via a via conductor layer 3v” and “via conductor layer 3v coupling the power supply plane 3dp and the power supply land 3p2(p)”),
wherein the external connection lines overlap the conductive layer in the vertical direction (Fig. 4 in this instance external connection line 3v between bonding finger 3p1(p) and conductive layer 3dp on the right side of semiconductor chip 2 overlaps the conductive layer 3dp in the vertical direction; ¶ 0054 “power supply bonding finger 3p1(p) is electrically connected with the power supply plane 3dp via the via conductor layer 3v”; ¶ 0048 “the power supply bonding finger 3p1(p) is electrically connected with the power supply plane 3dp via a via conductor layer 3v”).
Regarding Claim 13, Toyama discloses wherein:
the bonding fingers (3p1) are arranged repeatedly in a row (Fig. 1; ¶ 0044 “bonding fingers 3p1 are disposed around the semiconductor chip 2 along the four sides of the semiconductor chip 2”) in a first direction (X),
the lower conductive pattern (Mdp; Figs 4, 9; ¶ 0064 “copper film, and constitutes a power supply plane Mdp”) includes a through-hole (Fig. 9 the through-opening containing the unlabeled white portion of the insulating layer located below the conductive layer Mdp in the Y direction and extending half of the distance from the bottom surface of the conductive layer Mdp towards the bottom of the Y direction), and
a length of the through-hole in the first direction (X) is longer than (Fig. 9) a length of the through-hole in a second direction (Y), perpendicular to the first direction.
Regarding Claim 14, Toyama discloses
wherein the through-hole has a quadrangular shape, and
each of the bonding fingers has a lengthwise shape along the second direction.
Regarding Claim 17, Toyama discloses a semiconductor package (ED1, Fig. 4; ¶ 0040) comprising:
a substrate (3; Fig. 4; ¶ 0043 “substrate 3”) including:
bonding fingers (3p1; Figs. 4-5A; ¶ 0044 “bonding fingers 3p1 includes a power supply bonding finger 3p1(p), a ground bonding finger 3p1(g), and a signal bonding finger 3p1(s)”);
conductive lines (3w1; Figs. 4-5A; ¶ 0046); and
a conductive layer (3dp; Figs. 4, 6; ¶ 0048 “copper film, and constitutes a power supply plane 3dp” and “3dp is an island-like pattern when the wiring substrate 3 is assumed to be the sea”) including a through-opening (Fig. 6A the through-opening containing the unlabeled white portion of the insulating layer located below the conductive layer 3dp in the Y direction and extending half of the distance from the bottom surface of the conductive layer 3dp towards the bottom of the Y direction),
wherein each of the conductive lines is electrically connected to a corresponding one of the bonding fingers (Fig. 5A; ¶ 0046 “3w1 and the bonding finger 3p1 are formed as one body”); and
a first semiconductor chip (2; Fig. 4; ¶ 0041-0042 “semiconductor chip 2”) on the substrate (Fig. 4; ¶ 0056 “semiconductor chip 2 mounted on the upper surface 3a of the wiring substrate 3”) and electrically connected to the bonding fingers (Figs. 3-4; ¶ 0044 “a plurality of bonding fingers (terminals, chip mounting surface side terminals, electrodes, or bonding leads) 3p1 is formed electrically connected with the semiconductor chip 2” and “bonding finger 3p1 and the pad 2pd are electrically connected by a bonding wire BW”),
wherein:
the through-opening overlaps the bonding fingers in a vertical direction (Figs. 1, 6A in this instance the through-opening of Fig. 6A overlaps the bottom row of bonding fingers 3p1 of Fig. 1),
the bonding fingers are arranged repeatedly in a row (Fig. 1; ¶ 0044 “shown in FIG. 1, the bonding fingers 3p1 are disposed around the semiconductor chip 2 along the four sides of the semiconductor chip 2”) in a first direction (X), and
a length of the through-opening in the first direction is longer (the length of the through-opening in the X direction is longer) than a length of the through-opening in a second direction (Y), perpendicular to the first direction.
Regarding Claim 18, Toyama discloses
wherein the bonding fingers comprise:
a plurality of signal bonding fingers (3p1(s); Fig. 4; ¶ 0044 “signal bonding finger 3p1(s)”) through which a plurality of respective signals are transmitted or received by the first semiconductor chip (Figs. 1, 4; ¶ 0044 “signal bonding finger 3p1(s) is electrically connected with the signal pad 2pd(s) via a bonding wire BW”); and
a power bonding finger (3p1(p); Fig. 4; ¶ 0044 “power supply bonding finger 3p1(p)”) through which power is supplied to the first semiconductor chip (Figs. 1, 4, ¶ 0044 “power supply bonding finger 3p1(p) is electrically connected with the power supply pad 2pd(p) via a bonding wire BW”),
wherein the through-opening overlaps, in a vertical direction (Figs. 1, 6A in this instance the through-opening of Fig. 6A overlaps the bottom row of bonding fingers 3p1 of Fig. 1), a region between one of the signal bonding fingers and the power bonding finger, and a region between the plurality of signal bonding fingers (¶ 0044 “bonding fingers 3p1 includes a power supply bonding finger 3p1(p), a ground bonding finger 3p1(g), and a signal bonding finger 3p1(s)” therefore the through-opening overlaps a region between one of the signal bonding fingers and the power bonding finger, and a region between the plurality of signal bonding fingers).
Regarding Claim 21, Toyama discloses a semiconductor package (ED1; Fig. 4; ¶ 0040) comprising:
a substrate (3; Fig. 4; ¶ 0043 “substrate 3”) including:
bonding fingers (3p1; Figs. 4-5A; ¶ 0044 “bonding fingers 3p1 includes a power supply bonding finger 3p1(p), a ground bonding finger 3p1(g), and a signal bonding finger 3p1(s)”) arranged repeatedly in a row in a first direction (X);
conductive lines (3w1; Figs. 4-5A; ¶ 0046), wherein each of the conductive lines is electrically connected to a corresponding one of the bonding fingers (Figs. 4-5A; ¶ 0046 “3w1 and the bonding finger 3p1 are formed as one body”);
a conductive layer (3dp; Fig 4, 6A; ¶ 0048 “copper film, and constitutes a power supply plane 3dp” and “3dp is an island-like pattern when the wiring substrate 3 is assumed to be the sea”) overlapping a portion of the conductive lines in a vertical direction (Fig. 4; ¶ 0048 “third-layer wiring layer…constitutes a power supply plane 3dp”,
wherein the conductive layer includes a through-hole (Fig. 6A the through-hole containing the unlabeled white portion of the insulating layer located below the conductive layer 3dp in the Y direction) overlapping the bonding fingers in the vertical direction (Figs. 1, 6A in this instance the through-hole of Fig. 6A overlaps the bottom row of bonding fingers 3p1 of Fig. 1);
an insulating layer (Fig. 6A unlabeled white portion of the layer containing 3dp located below conductive layer 3dp in the Y direction), wherein at least portion of the insulating layer and the conductive layer are disposed at the same height level (Figs. 4, 6A; ¶ 0048 “third-layer wiring layer” insulating layer and conductive layer are both at the third-wiring layer);
external connection terminals (3p2(p); Fig. 4; ¶ 0054 “power supply land 3p2(p)”) disposed to be lower than the conductive layer (Fig. 4); and
external connection lines (3v; Fig. 4 in this instance the two external connection lines on the right side; ¶ 0054 “conductor layer 3v”) electrically connected to the external connection terminals (Fig. 4; ¶ 0054 “power supply bonding finger 3p1(p) is electrically connected with the power supply plane 3dp via the via conductor layer 3v and further electrically connected with the power supply land 3p2(p) via a via conductor layer 3v” and “power supply bonding finger 3p1(p) is electrically connected with the power supply plane 3dp via the via conductor layer 3v and further electrically connected with the power supply land 3p2(p) via a via conductor layer 3v”), the external connection lines not overlapping the through-hole in the vertical direction (Fig. 4 the external connection lines overlap conductive layer 3dp therefore they do not overlap the through-hole in the vertical direction;
bonding wires (BW; Fig. 4; ¶ 0056 “bonding wires BW”), each of which having a first end electrically connected to a corresponding one of the bonding fingers (Figs. 3-4; ¶ 0044 “bonding finger 3p1…electrically connected by a bonding wire BW”); and
a first semiconductor chip (2; Fig. 4; ¶ 0041-0042 “semiconductor chip 2”) on the substrate (Fig. 4; ¶ 0056 “semiconductor chip 2 mounted on the upper surface 3a of the wiring substrate 3”), the first semiconductor chip including pads (2pd; Figs. 3-4 ¶ 0042 “pads (electrodes or electrode pads) 2pd formed on the surface 2a side of the semiconductor chip 2”), wherein each of the pads is electrically connected to a second end of a corresponding one of the bonding wires (Figs. 3-4; ¶ 0044 “pad 2pd are electrically connected by a bonding wire BW”),
wherein the bonding fingers include:
a plurality of signal bonding fingers (3p1(s); Fig. 4; ¶ 0044 “signal bonding finger 3p1(s)”), through each of which a signal is transmitted or received by the first semiconductor chip (¶ 0044 “signal bonding finger 3p1(s) is electrically connected with the signal pad 2pd(s) via a bonding wire BW”); and
a power bonding finger (3p1(p); Fig. 4; ¶ 0044 “power supply bonding finger 3p1(p)”) through which power is supplied to the first semiconductor chip (¶ 0044 “power supply bonding finger 3p1(p) is electrically connected with the power supply pad 2pd(p) via a bonding wire BW”), and
wherein the through-hole overlaps, in the vertical direction (Figs. 1, 6A in this instance the through-hole of Fig. 6A overlaps the bottom row of bonding fingers 3p1 of Fig. 1), a region between the power bonding finger and an adjacent signal bonding finger and a region between the plurality of signal bonding fingers (¶ 0044 “bonding fingers 3p1 includes a power supply bonding finger 3p1(p), a ground bonding finger 3p1(g), and a signal bonding finger 3p1(s)” therefore the through-hole overlaps a region between the power bonding finger and an adjacent signal bonding finger and a region between the plurality of signal bonding fingers), and an area of the through-hole of the conductive layer is smaller than (Figs. 5B, 6A the area of the through-hole is smaller than the area of 3gp of Fig. 5B) an area of a remaining portion of the second conductive layer (3gp; Figs. 4, 5B; ¶ 0047 “ground plane 3gp is a solid pattern across the entire area of the wiring substrate 3 in a plan view”) in a plane view.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Toyama et al. (“Toyama”), US 2015/0237731, in view of Oh, US 2022/0208717.
Regarding Claim 7, Toyama discloses
the pads (2pd) and the bonding fingers (3p1) do not overlap each other in the vertical direction (Fig. 4).
Toyama does not disclose wherein the first semiconductor chip is attached to the upper surface of the substrate through an adhesive film.
Oh discloses wherein the first semiconductor chip (14; Fig. 9A; ¶ 0042 “first semiconductor device 14”) is attached to the upper surface (Fig. 9A) of the substrate (110) through an adhesive film (210; Fig. 9A; ¶ 0042 “die adhesive film 210”; ¶ 0058, ¶ 0117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Toyama to have wherein the first semiconductor chip is attached to the upper surface of the substrate through an adhesive film, as taught by Oh in order to secure the first semiconductor chip in the optimal location for electrically connecting the bonding wire 310 to the pads of the semiconductor chip, thereby improving the performance and reliability of the semiconductor package.
Regarding Claim 8, Toyama does not disclose further comprising
a second semiconductor chip on the substrate,
wherein the first conductive lines allow a signal to be transmitted or received between the first semiconductor chip and the second semiconductor chip.
Oh discloses further comprising
a second semiconductor chip (20c; Figs. 9A, 10A; ¶ 0127 “upper semiconductor chip 20c”) on the substrate (Figs. 9A, 10A; ¶ 0115 “upper semiconductor chips 20c stacked on the package substrate 100e”),
wherein the first conductive lines (120, 130, PAD1, PAD2, PADSH; Figs. 9A, 10A; ¶ 0070; ¶ 0118; ¶ 0125) allow a signal to be transmitted or received between (Figs. 9A, 10A; ¶ 0127 “lower semiconductor chip 10b can be electrically connected to the upper semiconductor chip 20c”) the first semiconductor chip (10b; Figs. 9A, 10A; ¶ 0127 “lower semiconductor chip 10b”) and the second semiconductor chip (Figs. 9A, 10A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Toyama to have further comprising a second semiconductor chip on the substrate, wherein the first conductive lines allow a signal to be transmitted or received between the first semiconductor chip and the second semiconductor chip, in order provide design flexibility and to increase the performance capabilities of the semiconductor package.
Regarding Claim 19, Toyama discloses wherein:
each of the conductive lines is connected to a corresponding one of the bonding fingers (Figs. 4, 5A; ¶ 0046 “3w1 and the bonding finger 3p1 are formed as one body”),
the conductive lines and the bonding fingers are disposed at the same height level ((Figs 4, 5A; ¶ 0046 “first-layer wiring layer is formed of…the bonding fingers 3p1 and a plurality of wirings 3w1”), and
an area of the through-opening (Fig. 6A in this instance a middle section of the bottom through-hole that overlaps a region between the bonding fingers) is smaller than an area of the conductive layer (Fig. 6A the area of 3dp) in a plane view (Fig. 6A in this instance an area of that middle section of the bottom through-hole is smaller than an area of conductive layer 3dp in a plan view).
Toyama does not disclose the first semiconductor chip is attached to an upper surface of the substrate through an adhesive film.
Oh discloses the first semiconductor chip (14; Fig. 9A; ¶ 0042 “first semiconductor device 14”) is attached to an upper surface (Fig. 9A) of the substrate (110) through an adhesive film (210; Fig. 9A; ¶ 0042 “die adhesive film 210”; ¶ 0058, ¶ 0117).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Toyama to have the first semiconductor chip is attached to an upper surface of the substrate through an adhesive film, as taught by Oh in order to secure the first semiconductor chip in the optimal location for electrically connecting the bonding wire 310 to the pads of the semiconductor chip, thereby improving the performance and reliability of the semiconductor package.
Allowable Subject Matter
Claims 9-11, 20, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 9, the prior art does not teach or render obvious wherein the first semiconductor chip is one of a plurality of first semiconductor chips at least partially overlapping each other in the vertical direction, the second semiconductor chip is one of a plurality of second semiconductor chips at least partially overlapping each other in the vertical direction, and a lowermost first semiconductor chip among the plurality of first semiconductor chips is mounted on the upper surface of the substrate with a flip-chip bonding structure. Therefore, the combination of the features of Claims 1, 8, and 9 is considered allowable.
Claims 10 and 11 incorporate all of the limitations of allowable Claim 9. Therefore, they are also allowable.
Regarding Claim 20, the prior art does not teach or render obvious further comprising a second semiconductor chip on the substrate, wherein: the conductive lines allow a signal to be transmitted or received between the first semiconductor chip and the second semiconductor chip, the first semiconductor chip is one of a plurality of first semiconductor chips at least partially overlapping each other in the vertical direction, the second semiconductor chip is one of a plurality of second semiconductor chips at least partially overlapping each other in the vertical direction, a lowermost second semiconductor chip among the plurality of second semiconductor chips is attached to an upper surface of the substrate through an adhesive film, and a lowermost first semiconductor chip among the plurality of first semiconductor chips is mounted on the upper surface of the substrate with a flip-chip bonding structure. Therefore, the combination of the features of Claims 17 and 20 is considered allowable.
Regarding Claim 22, the prior art does not teach or render obvious further comprising a second semiconductor chip on the substrate, wherein: the conductive lines allow a signal to be transmitted or received between the first semiconductor chip and the second semiconductor chip, the first semiconductor chip is one of a plurality of first semiconductor chips at least partially overlapping each other in the vertical direction, the second semiconductor chip is one of a plurality of second semiconductor chips at least partially overlapping each other in the vertical direction, a lowermost second semiconductor chip among the plurality of second semiconductor chips is attached to an upper surface of the substrate through an adhesive film, and a lowermost first semiconductor chip among the plurality of first semiconductor chips is mounted on the upper surface of the substrate with a flip-chip bonding structure. Therefore, the combination of the features of Claims 21 and 22 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. US 2010/0270689, Park et al US 2017/0278833, and Ha et al. US 2021/0327831 disclose a semiconductor package having a first semiconductor chip on a substrate, pads disposed on an upper surface of the first semiconductor chip, bonding fingers, and bonding wires electrically connected between the pads and bonding fingers.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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