Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Hong et al. (Us Patent Pub 20210057299 A1).
Regarding Claim 1, Hong teaches a semiconductor package comprising:
a substrate comprising first and second surfaces opposite to each other, wherein the substrate extends in first and second directions intersecting each other (Fig. 9, substrate 620 comprising a first surface (top surface of 620) and a second surface (bottom surface of 620) which are opposite each other. The substrate 620 extends in both a first direction (direction parallel to the top and bottom surfaces of the substrate) and a second direction (Paragraph 0130 teaches 630, which is part of the substrate, surrounds the side surfaces of 160. Therefore 630 extends into the page, which is the second direction. The first and second directions are orthogonal to each other, and therefore intersect each other));
a first semiconductor chip on the first surface of the substrate (Fig 9, first semiconductor chip 140 (Middle left portion of 140, see annotated figure below);
a second semiconductor chip on the first surface of the substrate and spaced apart from the first semiconductor chip in the first direction (Fig. 9, second semiconductor chip 140 (Leftmost portion of 140, see annotated figure below), which is spaced apart in the first direction from the first semiconductor chip);
and a dam structure at least partially surrounding the first semiconductor chip (Fig. 9, dam structure 630. 630 is on the left side of the first semiconductor chip, and therefore is partially surrounding the first semiconductor chip),
wherein the dam structure comprises first and second dam structures on the first surface of the substrate and spaced apart from each other in the first direction such that the first semiconductor chip resides therebetween, and wherein the first and second dam structures have different heights relative to the first surface of the substrate (Fig. 9, dam structure 630 comprises a first dam structure 632 and a second dam structure 634 on the first surface of the substrate. 632 and 634 are spaced apart in the first direction. Paragraph 0130 teaches the dam structure 630 is disposed to surround the entirety of structure 160. Therefore, 630 is disposed on both sides of 140 and 160, and therefore the first dam structure 632 and second dam structure 634 are spaced apart such that the first semiconductor chip 140 (see annotated figure) resides therebetween. The first dam structure 632 and the second dam structure 634 have different heights relative to each other (first dam structure 632 with height t1, and second dam structure 634 with height t2)).
PNG
media_image1.png
546
547
media_image1.png
Greyscale
Regarding Claim 2, Hong teaches the semiconductor package of claim 1, wherein the first dam structure has a first height relative to the first surface of the substrate (Hong, fig. 9, first dam structure 632 has a first height t1 relative to the first surface (top surface) of substrate 620),
wherein the second dam structure has a second height relative to the first surface of the substrate, wherein the second height is greater than the first height, and wherein the second dam structure is between the first semiconductor chip and the second semiconductor chip (Hong, fig. 9, teaches the second dam structure 634 has a second height t2 greater than the first height t1. The second dam structure 634 is located between the first semiconductor chip and the second semiconductor chip (see annotated figure above).
Regarding Claim 3, Hong teaches the semiconductor package of claim 1, wherein in a plan view of the semiconductor package, the dam structure extends to entirely surround the first semiconductor chip (Hong, paragraph 0130 teaches the dam structure 630 is disposed to surround the entirety of structure 160. Therefore, if viewed in plan view, the dam structure would entirely surround the first semiconductor chip).
Regarding Claim 4, Hong teaches the semiconductor package of claim 1, wherein the first and second dam structures are integral with the substrate (Hong, Fig. 9 teaches the first dam structure 632 and second dam structure 634 are formed into the substrate and are therefore integral with substrate 620).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claims 1-4 above, and further in view of Kim et al. (US Patent Pub 20210242101 A1).
Regarding Claim 5, Hong teaches the semiconductor package of claim 1.
Hong fails top specifically teach the semiconductor package wherein the dam structure further comprises third and fourth dam structures connecting the first and second dam structures to each other in a plan view of the semiconductor package, and wherein a distance in the second direction between the third dam structure and the first semiconductor chip is different from a distance in the second direction between the fourth dam structure and the first semiconductor chip.
However, Kim teaches a semiconductor package with a dam structure, and wherein the dam structure further comprises third and fourth dam structures connecting the first and second dam structures to each other in a plan view of the semiconductor package (Kim, figure 1 teaches a dam structure D having first through fourth dam structures connecting the first and second dam structures when viewed in plan view (see annotated figure below).
wherein a distance in the second direction between the third dam structure and the first semiconductor chip is different from a distance in the second direction between the fourth dam structure and the first semiconductor chip (Fig. 1, the distance W1 between the third dam structure and the first semiconductor chip is different from a distance W2 in the second direction between the fourth Dam structure and the first semiconductor chip (see annotated figure below).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kim into the method of Hong by forming the semiconductor package wherein the dam structure further comprises third and fourth dam structures connecting the first and second dam structures to each other in a plan view of the semiconductor package, and wherein a distance in the second direction between the third dam structure and the first semiconductor chip is different from a distance in the second direction between the fourth dam structure and the first semiconductor chip. The ordinary artisan would have been motivated to modify Hong in the manner set forth above for at least the purpose of securing a wide dispensing area of an underfill by arranging the dam structures to the desired dimensions (Kim, paragraph 0051).
Regarding Claim 6, Hong teaches the semiconductor package of claim 1.
Hong fails to teach the semiconductor package further comprising an underfill material layer is confined between the first surface of the substrate and the first semiconductor chip.
However, Kim teaches a semiconductor package device comprising an underfill material layer confined between the first surface of the substrate and the first semiconductor chip (Kim, fig. 2B teaches an underfill material layer 120 confined between the first surface (top surface) of substrate 102 and the first semiconductor chip 130).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kim into the method of Hong by forming the semiconductor package device comprising an underfill material layer confined between the first surface of the substrate and the first semiconductor chip. The ordinary artisan would have been motivated to modify Hong in the manner set forth above for at least the purpose of protecting the bump structures underneath the semiconductor chip (Kim, paragraph 0024).
Regarding Claim 7, Hong in view of Kim teaches the semiconductor package of claim 6, wherein the underfill material layer resides between the first and second dam structures (Kim, Fig. 2B teaches the underfill material layer 120 resides between the first dam structure Da (left side of 130) and second dam structure Da (right side of 130)).
Regarding Claim 8, Hong in view of Kim teaches the semiconductor package of claim 6, wherein the underfill material layer resides in a first trench extending from the first surface of the substrate into a portion of the substrate (Kim, fig. 2B. The first dam structure Da (left side of 130) and second dam structure Da (right side of 130) can be interpreted as being part of the substrate, therefore the underfill material layer resides in a first trench formed by the first and second dam structures extending from the first surface into the substrate).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Kim as applied to claims 5-8 above, and further in view of Saeki (US Patent Pub 20080237895 A1).
Regarding Claim 9, Hong in view of Kim teaches the semiconductor package of claim 6, wherein the underfill material layer is in contact with the first dam structure (Kim, fig. 2B, underfill 120 in contact with the first dam structure Da (left side of chip)).
Hong in view of Kim fails to teach the underfill material layer is in contact with the first dam structure and is spaced apart from the second dam structure.
However, Saeki teaches a semiconductor package device wherein underfill material layer is in contact with the first dam structure and is spaced apart from the second dam structure (Saeki, figs. 1A and 1B teaches an underfill material layer 15 that is in contact with the first dam structure (middle portion of dam structure 16) and spaced apart from the second dam structure (rightmost portion of 16 not in contact with 15)).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Saeki into the method of Hong in view of Kim by forming the semiconductor package wherein underfill material layer is in contact with the first dam structure and is spaced apart from the second dam structure. The ordinary artisan would have been motivated to modify Hong in view of Kim in the manner set forth above for at least the purpose of preventing the underfill material from flowing out of the substrate (Saeki, paragraph 0083).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Kim as applied to claims 5-8 above, and further in view of Yim et al. (US Patent Pub 20110275177 A1).
Regarding Claim 10, Hong in view of Kim teaches the semiconductor package of claim 1, wherein the first semiconductor chip comprises a third surface facing the first surface of the substrate, and a fourth surface opposite to the third surface (Kim, fig. 2A, first semiconductor chip 110 comprises a third surface (bottom surface of 110) facing the first surface (top surface) of the substrate 102, and a fourth surface (top surface of 110) opposite the third surface (See annotated figure below)),
wherein the second semiconductor chip comprises a fifth surface facing the first surface of the substrate, and a sixth surface opposite to the fifth surface (Kim, fig. 2A, second semiconductor chip 130 comprises a fifth surface (bottom surface of 130) facing the first surface (top surface) of the substrate 102, and a sixth surface (top surface of 130) opposite the fifth surface (see annotated figure below)),
wherein the first semiconductor chip is electrically connected to the substrate via bump residing between the first semiconductor chip and the first surface of the substrate (Kim, Fig 2A, first semiconductor chip 110 is electrically connected to the substrate via bumps 116 residing between 110 and the first surface (top surface) of substrate 102),
wherein the second semiconductor chip is electrically connected to the substrate via a semiconductor chip pad on the fifth surface of the second semiconductor chip and a bonding wire connected to the second semiconductor chip pad (Kim, Fig. 2A, second semiconductor chip 130 is electrically connected to the substrate via a semiconductor chip pad 132, which is on the fifth surface of the second semiconductor chip 130, and a bonding wire 134 connected to the second semiconductor chip pad 108).
Hong in view of Kim fails to specifically teach the first semiconductor chip comprises a first semiconductor chip pad on the third surface of the first semiconductor chip.
However, Yim teaches a semiconductor package device wherein the first semiconductor chip comprises a first semiconductor chip pad on the third surface of the first semiconductor chip (Yim, fig. 1A, first semiconductor chip 200 comprises a first semiconductor chip pad 215 on the third surface (bottom surface) of 215).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Yim into the method of Hong in view of Kim by forming the semiconductor package wherein the first semiconductor chip comprises a first semiconductor chip pad on the third surface of the first semiconductor chip. The ordinary artisan would have been motivated to modify Hong in view of Kim in the manner set forth above for at least the purpose of electrically connecting the semiconductor chip and the substrate (Yim, paragraph 0013).
PNG
media_image2.png
863
1608
media_image2.png
Greyscale
Claim(s) 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Yu et al. (US Patent Pub 20200135605 A1) and Kim (US Patent Pub 20210242101 A1).
Regarding Claim 11, Hong teaches a semiconductor package comprising:
a substrate comprising first and second surfaces opposite to each other, wherein the substrate extends in first and second directions intersecting each other (Hong, Fig. 9, substrate 620 comprising a first surface (top surface of 620) and a second surface (bottom surface of 620) which are opposite each other. The substrate 620 extends in both a first direction (direction parallel to the top and bottom surfaces of the substrate) and a second direction (Paragraph 0130 teaches 630, which is part of the substrate, surrounds the side surfaces of 160. Therefore 630 extends into the page, which is the second direction. The first and second directions are orthogonal to each other, and therefore intersect each other));
a semiconductor chip on the first surface of the substrate (Fig 9, first semiconductor chip 140 (Middle left portion of 140, see annotated figure below);
a second semiconductor chip, wherein the second semiconductor chip is spaced apart from the first semiconductor chip in the first direction (Fig. 9, second semiconductor chip 140 (Leftmost portion of 140, see annotated figure below), which is spaced apart in the first direction from the first semiconductor chip);
a bump electrically connecting the substrate and the second semiconductor chip to each other (Fig. 9, the second semiconductor chip (see annotated figure below) has bumps connecting the chip to the substrate);
and a dam structure on the first surface of the substrate, wherein the dam structure comprises portions spaced apart from each other, each portion having a height relative to the first surface of the substrate (Fig. 9, dam structure 630 comprising portions 632 and 634 spaced apart from each other, and each portion having a height (t1 and t2) relative to the first surface of the substrate),
wherein the height of a second portion of the dam structure on a central area of the substrate is greater than the height of a first portion of the dam structure on a peripheral area of the substrate (Fig. 9, height (t2) of the second portion 634 of the dam structure 630 on a central area of the substrate 620 us greater than a height t1 of a first portion 632 of the dam structure 630).
Hong fails to teach a semiconductor chip stack comprising a plurality of semiconductor chips on the first surface of the substrate, wherein the semiconductor chip stack is spaced apart from the semiconductor chip in the first direction.
However, Yu teaches a semiconductor package having a semiconductor chip stack comprising a plurality of semiconductor chips on the first surface of the substrate, wherein the semiconductor chip stack is spaced apart from the semiconductor chip in the first direction (Yu, fig. 7, semiconductor chip stack 401 (right side of device) comprising a plurality of semiconductor chips 403A-H. The semiconductor chip stack 401 (right side of device) is spaced apart from semiconductor chip 401 (left side of device) in the first direction).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Yu into the method of Hong by forming the semiconductor package having a semiconductor chip stack comprising a plurality of semiconductor chips on the first surface of the substrate, wherein the semiconductor chip stack is spaced apart from the semiconductor chip in the first direction. The ordinary artisan would have been motivated to modify Hong in the manner set forth above for at least the purpose of reduce the physical size of semiconductor devices (Yu, paragraph 0004).
While Hong in view of Yu teaches the semiconductor package described above, they fail to teach the device having a bonding wire electrically connecting the substrate and the semiconductor chip stack to each other, and wherein the second first dam structure is adjacent the bond wire and located on a peripheral area of the substrate.
However, Kim teaches a semiconductor package having a bonding wire electrically connecting the substrate and the semiconductor chip stack to each other, and wherein the first dam structure is adjacent the bond wire and located on a peripheral area of the substrate (Kim, fig. 2A, bonding wire 134 connects the substrate 102 and the semiconductor chip stack (comprised of chips 110 and 130) to each other. The first dam structure Da is adjacent to the bonding wire and located on a peripheral area (the peripheral area is interpreted as the area to the right of chip stack 110/130) of the substrate 102).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Kim into the method of Hong in view of Yu by forming the semiconductor package having a bonding wire electrically connecting the substrate and the semiconductor chip stack to each other, and wherein the first dam structure is adjacent the bond wire and located on a peripheral area of the substrate (Kim, fig. 2A, bonding wire 134 connects the substrate 102 and the semiconductor chip stack. The ordinary artisan would have been motivated to modify Hong in view of Yu in the manner set forth above for at least the purpose of utilizing the dam structure to prevent bonding pads to be covered by the underfill (Kim, paragraph 0003).
Regarding Claim 12, Hong in view of Kim and Yu teaches the semiconductor package of claim 11, wherein the dam structure comprises a first dam structure on the peripheral area of the substrate, and a second dam structure on the central area of the substrate (Hong, fig. 9. Dam structure 630 comprises a first dam structure 632 on the peripheral area (paragraph 0130 teaches dam structure 630 surrounds 160, therefore another portion of 630 is present on the right side of 160. The peripheral area of the substrate can be defined as being to the right of 160, therefore the first dam structure 632 is located on the right side of 160/peripheral area of the substrate) and a second dam structure 634 on the central area (area between the second semiconductor chip and the first semiconductor chip) of the substrate))
wherein the first dam structure has a first height relative to the first surface of the substrate (Hong, fig. 9 shows 632 has a first height t1 relative to the first surface (top surface) of the substrate 620),
wherein the second dam structure has a second height relative to the first surface of the substrate, wherein the second height is greater than the first height (Hong, fig. 9 teaches second dam structure 634 having a second height t2 relative to the first surface (top surface) of the substrate 620. Fig. 9 also teaches t2 is greater than t1).
Regarding Claim 13, Hong in view of Kim and Yu teaches the semiconductor package of claim 11, wherein in a plan view of the semiconductor package, the dam structure extends to entirely surround the semiconductor chip (Kim, fig. 1 teaches that in plan view, the dam structure D extends to entirely surround the semiconductor chip 110).
Regarding Claim 14, Hong in view of Kim and Yu teaches the semiconductor package of claim 12, wherein the dam structure comprises an insulating material (Hong, paragraph 0050 teaches 121 (which is the part of the substrate 120 the dam structure is composed of) is an insulating layer that may be formed of an insulating material).
Regarding Claim 15, Hong in view of Kim and Yu teaches the semiconductor package of claim 14, further comprising an underfill material layer residing between the first surface of the substrate and the semiconductor chip, and at least partially surrounds the bump (Kim, fig. 2A teaches an underfill material layer 120 residing between the first surface (top surface) of the substrate 102 and semiconductor chip 110, and surrounds bump structures 116).
Regarding Claim 16, Hong in view of Kim and Yu teaches the semiconductor package of claim 15, wherein the underfill material layer is confined between the first and second dam structures (Kim, fig. 2A teaches the underfill material layer 120 is confined between the first dam structure Da and the second dam structure Db).
Regarding Claim 17, Hong in view of Kim and Yu teaches the semiconductor package of claim 15, wherein the underfill material layer resides in a first trench extending from the first surface of the substrate into a portion of the substrate (Kim, Fig. 2A teaches first and second dam structures Da and Db, respectively, and paragraph 0045 teaches the dam structures can be formed of a dielectric material. Paragraph 0052 of Applicant’s instant specification teaches the protective film 111 (the structure the dam is formed of) comprises a dielectric material and is part of the substrate. Therefore, the dam structure of Kim can be interpreted as part of the substrate. Further, the dam structure comprising Da and Db forms a first trench into the substrate. Underfill material layer 120 resides in the first trench formed into the substrate defined by Da and Db).
Regarding Claim 18, Hong in view of Kim and Yu teaches the semiconductor package of claim 17, wherein a depth of the first trench increases as the first trench extends toward the bonding wire (Kim, fig. 2A teaches a first trench defined by the first dam structure Da and the second dam structure Db. Hong, fig. 9 teaches the first dam structure 632 has a height t1 and the second dam structure 634 has a height t2, which is greater than t1. Therefore, the combination of Hong and Kim teach a trench structure defined by dam structures, wherein the dam structures comprise a first and second dam structure, and wherein the height of the second dam structure is greater than the height of the first dam structure. Further, the combination can yield the device of Kim being arranged such that the dam structure Da adjacent to the bonding wire 134 has a greater height than second dam structure Db, yielding a trench wherein a depth of the first trench increases as the first trench extends toward the bonding wire).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yu.
Regarding Claim 19, Kim teaches a semiconductor package comprising:
a substrate comprising first and second surfaces opposite to each other, wherein a first trench extends into a portion of the substrate from the first surface (Kim, fig. 2A, substrate 102 comprising a first surface (top surface of 102) and a second surface (bottoms surface of 102), wherein a first trench extends into a portion of the substrate from the first surface (Fig. 2A teaches first and second dam structures Da and Db, respectively, and paragraph 0045 teaches the dam structures can be formed of a dielectric material. Paragraph 0052 of Applicant’s instant specification teaches the protective film 111 (the structure the dam is formed of) comprises a dielectric material and is part of the substrate. Therefore, the dam structure of Kim can be interpreted as part of the substrate. Further, the dam structure comprising Da and Db forms a first trench into the substrate from the first surface));
a semiconductor chip on the first surface of the substrate (Kim, Fig. 2A, semiconductor chip 110 on the first surface of substrate 102);
a bump electrically connecting the substrate and the semiconductor chip to each other (Kim, fig. 2A, bump 116 electrically connecting the substrate 102 and the semiconductor chip 110 to each other);
a bonding wire electrically connecting the substrate and the semiconductor chip stack to each other (Kim, fig. 2A, bonding wire 134 electrically connecting the substrate 102 and a second semiconductor chip 130 to each other);
a dam structure on the first surface of the substrate, wherein the dam structure comprises portions spaced apart from each other (Kim, fig. 2A, dam structure Da/Db comprising portions Da and Db spaced apart from each other);
and an underfill material layer extending between the first surface of the substrate and the semiconductor chip, and extending in the first trench (Kim, Fig. 2A, underfill material layer 120 extending between the first surface (top surface) of the substrate 102 and the semiconductor chip 110, and extending in the first trench (trench formed by Db and Da)).
Kim fails to teach a semiconductor chip stack comprising a plurality of semiconductor chips on the first surface of the substrate, wherein the semiconductor chip stack is spaced apart from the semiconductor chip.
However, Yu teaches a semiconductor package having a semiconductor chip stack comprising a plurality of semiconductor chips on the first surface of the substrate, wherein the semiconductor chip stack is spaced apart from the semiconductor chip (Yu, fig. 7 teaches a semiconductor chip stack 401/403A-H (right side of the device) comprising a plurality of semiconductor chips 403A-H of the first surface (top surface) of substrate 101 and spaced apart from second semiconductor chip 401 (left hand side).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Yu into the method of Kim by forming the semiconductor package having having a semiconductor chip stack comprising a plurality of semiconductor chips on the first surface of the substrate, wherein the semiconductor chip stack is spaced apart from the semiconductor chip. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of reducing the physical size of semiconductor devices (Yu, paragraph 0004).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yu as applied to claim 19 above, and further in view of Hong.
Regarding Claim 20, Kim in view of Yu teaches the semiconductor package of claim 19, wherein a dam structure (Da) resides adjacent to the bonding wire 134 on a central area (the central area of the substrate 102 is interpreted as being located between structure Db and bonding wire 134).
Kim in view of Yu fails to specifically teach the semiconductor package wherein a height of a portion of the dam structure residing on a central area of the substrate adjacent to the bonding wire is greater than a height of a portion of the dam structure residing on a peripheral area of the substrate.
However, Hong teaches a semiconductor package wherein a height of a portion of the dam structure residing on a central area of the substrate adjacent to the bonding wire is greater than a height of a portion of the dam structure residing on a peripheral area of the substrate (Hong, Fig. 9 teaches a dam structure 630 comprising a first portion 632 having a first height t1, and a second portion 634 having a second height t2 greater than the first height. Paragraph 0130 teaches dam structure 630 surrounds the structure 160, therefore 630 is also disposed to the right of 160. The peripheral area of the substrate can be interpreted as the area to the right of 160, and the central area of the substrate can be interpreted as the area between the leftmost portion of 140 and the central left portion of 140. Therefore, a height t2 of a portion 634 located in the central area of substrate 102 is greater than a height t1 of a portion 632 residing on a peripheral area of the substrate 102).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Hong into the method of Kim in view of Yu by forming the semiconductor package wherein a height of a portion of the dam structure residing on a central area of the substrate adjacent to the bonding wire is greater than a height of a portion of the dam structure residing on a peripheral area of the substrate. The ordinary artisan would have been motivated to modify Kim in view of Yu in the manner set forth above for at least the purpose of preventing the encapsulant material from flowing over the dam structure (Hong, paragraph 0135).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICENTE R GONZALES whose telephone number is (571)272-3365. The examiner can normally be reached Monday - Friday 7:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights