CTNF 18/772,608 CTNF 97902 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) was submitted on 07/15/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification 07-29 AIA The disclosure is objected to because of the following informalities: Paragraph [0024] states “Figures 1DA – 1T are cross-sectional side views…”. It appears that the figures being referred to are figures 1D to 1T. The paragraph should be corrected to state the correct figures being described . Appropriate correction is required. 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 07-34-05 AIA Claim 20 recites the limitation " the recessed conductive layer " in line 1 and 2 of claim 20 . There is insufficient antecedent basis for this limitation in the claim. Claim 20 states “The interconnection structure of claim 19 , wherein a top surface of the recessed conductive layer …”. Claim 20 depends on claim 19 and 15, which include “ a conductive layer ”. It is unclear if the conductive layer in claims 15 and 19 are the same conductive layer as the recessed conductive layer in claim 20, as claim 15 and 19 do not refer to the conductive layer as recessed or as a recessed conductive layer. Claim 16 mentions the top surface of the conductive layer being recessed, but claim 20 does not depend on claim 16 and claim 16 refers to the conductive layer as “the conductive layer” and not “a recessed conductive layer”. As it is unclear what conductive layer is being referred to in claim 20 and if the conductive layer is recessed or not in claim 20, there are multiple interpretations present and claim 20 is rejected as being indefinite. For the purpose of compact prosecution, examiner is interpreting claim 20 as stating “…wherein a top surface of the conductive layer is lower than the co-planar top surface of the capping layer, the support layer, and the dielectric fill”. This appears to be consistent with the terminology used in claims 15 and 19. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 1 – 4, 6 – 11, 13, 15, and 17 - 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20210193566 A1 hereinafter Lo . 07-15-02-aia The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. For claim 1, Lo teaches “An interconnection structure (fig. 20) comprising: a dielectric layer (fig. 20 numeral 104); a first conductive feature disposed in the dielectric layer (fig. 20 numeral 106); a conductive layer comprising a first portion and a second portion (fig. 20 numeral 114), wherein the first portion of the conductive layer is disposed over the first conductive feature, and the second portion of the conductive layer is disposed over the dielectric layer (fig. 20 numeral 114 shows the conductive layer having a portion over the conductive feature 106 and a portion over the dielectric layer 104); a capping layer having a first portion, a second portion opposing the first portion, and a third portion connecting the first portion and the second portion (fig. 20 numeral 116), wherein the first portion of the capping layer is in contact with the first portion of the conductive layer (fig. 20 numeral 116 is shown contacting conductive layer 114 over the conductive contact 106), the second portion of the capping layer is in contact with the second portion of the conductive layer (fig. 20 numeral 116 is shown contacting conductive layer 114 over the dielectric layer 104), and the third portion of the capping layer is in contact with the dielectric layer (fig. 20 shows the third portion connecting the first and second portions of capping layer 116 is in contact with the dielectric layer 104); a support layer in contact with the first and second portions of the capping layer (fig. 20 numeral 118), wherein an air gap is defined by the support layer, the first portion of the capping layer, the second portion of the capping layer, and the third portion the capping layer (fig. 20 numeral 112); and an etch stop layer disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer (fig. 20 numeral 124).” For claim 2, Lo teaches “The interconnection structure of claim 1, wherein the air gap is disposed between the first portion of the conductive layer and the second portion of the conductive layer (fig. 20 numeral 112 shows the air gap between conductive layer portions 114).” For claim 3, Lo teaches “The interconnection structure of claim 1, further comprising: a dielectric fill disposed over the air gap and in contact with the support layer (fig. 20 numeral 120).” For claim 4, Lo teaches “The interconnection structure of claim 3, wherein the etch stop layer is further disposed over the dielectric fill (fig. 20 numeral 124).” For claim 6, Lo teaches “The interconnection structure of claim 1, further comprising: a dielectric material disposed over the second portion of the conductive layer, the second portion of the capping layer and the support layer (fig. 20 numeral 126); and a second conductive feature disposed in the dielectric material in contact with the first portion of the conductive layer and the first portion of the capping layer (fig. 20 numeral 130 and 128).” Examiner is interpreting the term “contact” to mean to be in either direct or indirect contact based on the definition given in the immediate invention specification (immediate specification; Par. [0009]). In Lo, the second conductive feature is in indirect contact with the capping layer. For claim 7, Lo teaches “The interconnect structure of claim 6, further comprising: a barrier layer disposed between the second conductive feature and the first portion of the conductive layer, and in contact with the second conductive feature, the first portion of the conductive layer and the first portion of the capping layer (fig. 20 numeral 122).” Examiner is interpreting the term “contact” to mean to be in either direct or indirect contact based on the definition given in the immediate invention specification (immediate specification; Par. [0009]). For claim 8, Lo teaches “The interconnect structure of claim 6, wherein the second conductive feature is further in contact with the support layer (fig. 20 numeral 130 and 128).” Examiner is interpreting the term “contact” to mean to be in either direct or indirect contact based on the definition given in the immediate invention specification (immediate specification; Par. [0009]). In Lo, the second conductive feature is in indirect contact with the support layer. For claim 9, Lo teaches “The interconnection structure, comprising: a dielectric layer (fig. 20 numeral 104); a first conductive feature disposed in the dielectric layer (fig. 20 numeral 106); a conductive layer disposed over the first conductive feature and the dielectric layer (fig. 20 numeral 114); a capping layer embedded in the conductive layer, wherein a sidewall of the capping layer is in contact with the conductive layer, and a bottom surface of the capping layer is in contact with the dielectric layer (fig. 20 numeral 116); a support layer in contact with the capping layer (fig. 20 numeral 118), wherein an air gap is defined by the support layer and the capping layer (fig. 20 numeral 112); a dielectric fill disposed over the air gap and in contact with the support layer (fig. 20 numeral 120); and a metal oxide layer disposed over the dielectric fill, the support layer, and the capping layer (fig. 20 numeral 122; Par. [0027]).” For claim 10, Lo teaches “The interconnection structure of claim 9, further comprising: an etch stop layer disposed over the conductive layer, the capping layer and the metal oxide layer (fig. 20 numeral 124). For claim 11, Lo teaches “The interconnection structure of claim 10, further comprising a dielectric material disposed over the etch stop layer (fig. 20 numeral 126); and a second conductive feature disposed in the dielectric material in contact with the conductive layer, the capping layer and the metal oxide layer (fig. 20 numeral 130 and 128).” For claim 13, Lo teaches “The interconnection structure of claim 9, wherein a top surface of the conductive layer is lower than a top surface of the metal oxide layer (fig. 20 numeral 114 shows the conductive layer having a lower top surface than the metal oxide layer 122).” For claim 15, Lo teaches “An interconnection structure (fig. 20) comprising: a conductive layer (fig. 20 numeral 114) disposed over a dielectric layer (fig. 20 numeral 104), wherein the conductive layer includes a first portion and a second portion (fig. 20 shows conductive layer 114 separated into multiple portions); a capping layer disposed on the dielectric surface of the dielectric layer between the first and second portions of the conductive layer and a conductive surface of the conductive layer (fig. 20 numeral 116); a support layer disposed on the capping layer (fig. 20 numeral 118), wherein an air gap is disposed between the first and second portions of the conductive layer and between the support layer and the capping layer (fig. 20 numeral 112); a dielectric fill disposed on the support layer (fig. 20 numeral 120); an etch stop layer disposed over the conductive layer, the capping layer, the support layer and the dielectric fill (fig. 20 numeral 124); a dielectric material disposed on the etch stop layer (fig. 20 numeral 126); and a conductive feature disposed through the dielectric material and the etch stop layer to a top surface of a portion of the conductive layer (fig. 20 numeral 130 and 128).” For claim 17, Lo teaches “The interconnection structure of claim 15, further comprising a metal oxide layer disposed on the capping layer, the support layer and the dielectric fill (fig. 20 numeral 122; Par. [0027]).” For claim 18, Lo teaches “The interconnection structure of claim 17, wherein the etch stop layer is disposed on the metal oxide layer (fig. 20 shows etch stop layer 124 over the metal oxide layer 122).” For claim 19, Lo teaches “The interconnection structure of claim 15, wherein the dielectric fill is disposed in the support layer (fig. 20 numeral 120), and the capping layer, the support layer and the dielectric fill substantially have a co-planar top surface (fig. 20 shows the capping layer 116, the support layer 118, and the dielectric fill 120 as having co-planar top surfaces).” Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 14 is/are rejected under 35 U.S.C. 103 as being obvious over US 20210193566 A1 hereinafter Lo in further view of US 20220223465 A1 hereinafter Huang. The applied references have a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). For claim 14, Lo teaches all of claim 13. Lo is silent regarding a barrier layer disposed between the second conductive feature and the conductive layer, and in contact with the conductive feature, the conductive layer, the capping layer and the metal oxide layer. Huang teaches an interconnection structure (Huang, fig. 2R) with a conductive feature (fig. 2R numeral 350) and a conductive layer (fig. 2R numeral 312) with a capping layer (fig. 2R numeral 320) and a metal oxide layer (fig. 2R numeral 338). Huang also has a barrier layer disposed between the conductive feature and the conductive layer that is also in contact with the conductive feature, the conductive layer, the capping layer and the metal oxide layer (fig. 2R numeral 349). 07-21-02-aia It would have been obvious before the effective filing date of the immediate invention to combine the barrier layer in Huang with the second conductive feature in Lo in order to reduce line leakage within the device (Huang, Par. [0029 – 0032]). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 5, 12, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. For claim 5, 12, and 16, the top surface of the conductive layer and the conductive layer portions in Lo appears to be at the same level or co-planar with the dielectric fill and not below the top surface of the dielectric fill. 07-43-02 AIA Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. For claim 20, the top surface of the conductive layer in Lo is shown to be at the same level or co-planar to the top surfaces of the capping layer, the support layer, and the dielectric fill. Lo appears to teach away from the top surface of the conductive layer being lower than the co-planar top surface of the capping layer, the support layer, and the dielectric fill. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.T.N./Examiner, Art Unit 2815 /MONICA D HARRISON/Primary Examiner, Art Unit 2815 Application/Control Number: 18/772,608 Page 2 Art Unit: 2815 Application/Control Number: 18/772,608 Page 3 Art Unit: 2815 Application/Control Number: 18/772,608 Page 4 Art Unit: 2815 Application/Control Number: 18/772,608 Page 5 Art Unit: 2815 Application/Control Number: 18/772,608 Page 6 Art Unit: 2815 Application/Control Number: 18/772,608 Page 7 Art Unit: 2815 Application/Control Number: 18/772,608 Page 8 Art Unit: 2815 Application/Control Number: 18/772,608 Page 9 Art Unit: 2815 Application/Control Number: 18/772,608 Page 10 Art Unit: 2815 Application/Control Number: 18/772,608 Page 11 Art Unit: 2815
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