DETAILED ACTION
A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE THREE MONTHS FROM THE MAILING DATE OF THIS COMMUNICATION.
Responsive to the application filed July 15, 2024 and the preliminary amendment filed July 29, 2024. This action is non-final.
Claims 1-14 are pending and have been examined. Claims 1-14 are rejected. No claim is allowed.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending and have been examined on the merits.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
Acknowledgment is made of applicant's claim for domestic benefit under 35 U.S.C. § 120.
This application is a continuation of U.S. Application No. 17/704,618, filed March 25, 2022, now U.S. Patent No. 12,126,263, which is a continuation of International Application No. PCT/JP2020/020053, filed May 21, 2020.
The domestic benefit claim is acknowledged and is proper. No double patenting rejection is made over U.S. Patent No. 12,126,263.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. § 119(a)-(d).
The certified copy of Japanese Application No. 2019-176427, filed September 27, 2019, has been electronically retrieved on 08/02/2024.
Information Disclosure Statements
The information disclosure statements submitted on the following dates have been considered by the examiner. Copies of the annotated PTO/SB/08 forms are attached.
July 15, 2024
September 13, 2024
April 7, 2025
January 9, 2026
April 21, 2026
June 8, 2026
Claim Interpretation
The claims contain several ambiguities that are treated in the rejection under 35 U.S.C. § 112(b) below. Pursuant to MPEP 2173.06, the prior art rejections are applied to the claims as best understood in view of the specification.
As best understood, claim 1 requires an insulating layer; five wiring patterns on a surface of that layer; a first vertical transistor having source and control electrodes on a front surface and a drain electrode on a back surface, the back-surface electrode being on the first wiring pattern; a second vertical transistor of the same construction with its back-surface electrode on the second wiring pattern; the first front-surface electrode connected to the third wiring pattern by a plurality of first wires and to the fourth wiring pattern by a second wire; the second front-surface electrode connected to the first wiring pattern by a plurality of third wires and connected to the fifth wiring pattern; and each of the five wiring patterns connected to a corresponding external extraction terminal.
As best understood, claim 8 requires the same insulating layer, five patterns, and two vertical transistors, except that the first front-surface electrode is connected to the third wiring pattern by a plurality of first wires, and the second front-surface electrode is connected to the first wiring pattern by a plurality of third wires and to the fifth wiring pattern by a fourth wire. The fourth wiring pattern is recited as formed and as having a terminal. As best understood in view of the specification, that fourth wiring pattern is a source-sense or gate pattern.
As best understood, claim 12 is intended to depend from claim 8.
Reference numerals from the specification (D4, D1, S4, SSL4, SL1, Q4, Q1, W2, W3) are used only for readability and are not imported as unclaimed limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or, for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Regarding claim 1, the limitation "a fifth a first wiring pattern" is indefinite. The claim recites "a first wiring pattern, a second wiring pattern, a third wiring pattern, a fourth wiring pattern and a fifth a first wiring pattern." It is unclear whether five wiring patterns are required, or whether the last-recited pattern is a second instance of the first wiring pattern. The later recitation "the fifth wiring pattern" lacks a clear antecedent. Clarification is required. For purposes of examination, the phrase is treated as intending to recite a fifth wiring pattern, distinct from the first through fourth wiring patterns.
Regarding claim 1, the limitation "the second front surface electrode ... is connected to the fifth wiring pattern" is indefinite. The claim recites a connecting structure (wires) for the other source connections. No connecting structure is recited for the connection of the second front surface electrode to the fifth wiring pattern. It is unclear whether that connection is made by a wire, by direct attachment, or by identity with another recited node. Clarification is required. For purposes of examination, the connection is treated as a wire connection consistent with the specification.
Regarding claim 1, the limitation "a insulating layer" requires clarification as to whether one insulating layer is required. The phrase is treated as "an insulating layer."
Claims 2-7 and 11 are rejected as being indefinite because they depend from indefinite claim 1 and do not cure the indefiniteness of claim 1.
Regarding claim 3, the limitation "the first wiring pattern the first wiring pattern is connected to an output terminal" is indefinite. The repeated phrase makes it unclear whether one connection or two connections are required, and which structure is the antecedent for "the first wiring pattern." Clarification is required.
Regarding claim 3, the limitation "a high-terminal" is indefinite. The term has no established meaning as written and has no antecedent basis. It is unclear whether applicant intends a high-side terminal, a power terminal, or some other terminal. Clarification is required. For purposes of examination, the phrase is treated as a high-side terminal.
Regarding claim 6, the limitation "the fourth wire" lacks antecedent basis. Claim 6 depends from claim 1. A fourth wire is first introduced in claim 5. It is therefore unclear which structure in claim 1 is "the fourth wire," and it is unclear which current paths are being compared in the recited inductance relationship. Clarification is required.
Regarding claim 8, the limitation "a fifth a first wiring pattern" is indefinite for the same reasons set forth with respect to claim 1. Clarification is required. The phrase is treated as intending to recite a fifth wiring pattern.
Regarding claim 8, the claim recites that a fourth wiring pattern is formed on the insulating layer and that the fourth wiring pattern is connected to a corresponding external extraction terminal. The body of the claim does not connect the fourth wiring pattern to the first transistor or to the second transistor. It is unclear what function the fourth wiring pattern performs in the claimed power module, and it is unclear whether the fourth wiring pattern is a source-sense pattern, a gate pattern, or an electrically unused pattern. Clarification is required. As best understood in view of the specification, the fourth wiring pattern is treated as a source-sense or gate pattern already present on the substrate.
Regarding claim 8, the limitation "via a fourth wires" is indefinite. It is unclear whether one fourth wire or a plurality of fourth wires is required. Clarification is required. The phrase is treated as a fourth wire.
Regarding claim 8, the limitation "a insulating layer" requires clarification for the same reasons set forth with respect to claim 1.
Claims 9, 10, and 14 are rejected as being indefinite because they depend from indefinite claim 8 and do not cure the indefiniteness of claim 8.
Regarding claim 11, the limitation "the forth wiring pattern" is indefinite. It is unclear whether "forth" is intended to refer to "the fourth wiring pattern" of claim 1 or to a different pattern. Claim 11 also appears to repeat the subject matter of claim 4. Clarification is required. The phrase is treated as "the fourth wiring pattern."
Regarding claim 12, the claim is incomplete and is therefore indefinite. Claim 12 does not include a preamble identifying the invention, does not include a phrase such as "The power module according to claim ___," and recites "the insulating layer," "the third wiring pattern," and "the first wiring pattern" without any antecedent basis in claim 12 itself. It is unclear whether claim 12 is intended to be independent or dependent, and if dependent, from which claim it depends. Clarification is required. For purposes of examination, claim 12 is treated as intended to depend from claim 8.
Claim 13 is rejected as being indefinite because it depends from indefinite claim 12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2018/186353 A1 to Rohm Co., Ltd. ("Rohm"; published October 11, 2018).
U.S. Patent No. 10,734,911 and U.S. Patent Application Publication No. 2020/0035656 A1 are the U.S. counterpart of WO 2018/186353 A1 and are cited only as an English-language description of the same disclosure. The applied reference is WO 2018/186353 A1. U.S. Application No. 16/591,183 was filed October 2, 2019 and is not applied as prior art under 35 U.S.C. 102(a)(2).
The mapping below is applied to claim 1 as best understood in view of the rejection under 35 U.S.C. § 112(b). In particular, "a fifth a first wiring pattern" is treated as a fifth wiring pattern, and the connection of the second front surface electrode to the fifth wiring pattern is treated as a wire connection.
Regarding independent claim 1, Rohm teaches a power module comprising:
an insulating layer on a surface of which wiring patterns are formed
(ceramic / insulating substrate having electrode patterns formed on a surface thereof; Abstract; Figs. 5-9, 15-18);
a first transistor having a first front surface electrode and a first control electrode on a front surface thereof and a first back surface electrode on a back surface thereof, the first back surface electrode being disposed on and electrically connected to a first wiring pattern
(power transistor Q4; drain of Q4 disposed on drain pattern D4; source and gate of Q4 connected by wires from the upper face of Q4; Figs. 5-9, 15-18);
a second transistor having a second front surface electrode and a second control electrode on a front surface thereof and a second back surface electrode on a back surface thereof, the second back surface electrode being disposed on and electrically connected to a second wiring pattern
(power transistor Q1; drain of Q1 disposed on drain pattern D1; source and gate of Q1 connected by wires from the upper face of Q1; Figs. 5-9, 15-18);
wherein the first front surface electrode is connected to a third wiring pattern via a plurality of first wires
(source of Q4 connected to source pattern S4 by a plurality of source wires SW4; Figs. 5-9, 15-18);
and is connected to a fourth wiring pattern via a second wire
(source of Q4 connected to source-sense pattern SSP4 by source-sense wire SSW4; Figs. 5-9, 15-18);
the second front surface electrode is connected to the first wiring pattern via a plurality of third wires
(source of Q1 connected to drain / output pattern D4 by a plurality of source wires SW1; Figs. 5-9, 15-18);
and is connected to a fifth wiring pattern
(source of Q1 connected to source-sense pattern SSP1 by source-sense wire SSW1; Figs. 5-9, 15-18);
each of the first wiring pattern, the second wiring pattern, the third wiring pattern, the fourth wiring pattern and the fifth wiring pattern is connected to a corresponding external extraction terminal
(D4 to output terminal O; D1 to high-side terminal P; S4 to low-side terminal N; SSP4 to source-sense terminal SST4; SSP1 to source-sense terminal SST1; Figs. 5-9, 15-18).
Rohm does not use the claim labels "first wiring pattern," "second wiring pattern," "third wiring pattern," "fourth wiring pattern," and "fifth wiring pattern." Those labels do not change the structure Rohm already discloses. Drain pattern D4 is the first wiring pattern. Drain pattern D1 is the second wiring pattern. Source pattern S4 is the third wiring pattern. Source-sense pattern SSP4 is the fourth wiring pattern. Source-sense pattern SSP1 is the fifth wiring pattern.
Rohm also does not use the claim words "front surface electrode" and "back surface electrode." Rohm still teaches those electrodes. Q1 and Q4 are vertical power MOSFETs mounted drain-down on D1 and D4. The drain of each device is the electrode on the lower face of the die and is the electrode Rohm disposes on the drain pattern. That drain is the claimed back surface electrode. The source and the gate of each device are the electrodes on the upper face of the die and are the electrodes Rohm connects by wires SW and SSW. The source is the claimed front surface electrode. The gate is the claimed control electrode.
Accordingly, as best understood: the first front surface electrode is the source of Q4; the first control electrode is the gate of Q4; the first back surface electrode is the drain of Q4 on D4; the second front surface electrode is the source of Q1; the second control electrode is the gate of Q1; and the second back surface electrode is the drain of Q1 on D1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to read the Rohm half-bridge of Figures 5-9 and 15-18 on claim 1 as mapped above. Rohm already provides the five patterns, the drain-down mounting of Q1 and Q4, the source wires SW, the source-sense wires SSW, and the external terminals. The claim wording differs from Rohm's wording. The module Rohm discloses is the module claim 1 recites.
Regarding claim 2, Rohm teaches the power module according to claim 1, as best understood, wherein
the first transistor and the second transistor are composed of SiC MISFET, respectively
(Rohm identifies SiC based MOSFETs as suitable devices for Q1 and Q4; a SiC MOSFET is a SiC metal-insulator-semiconductor field-effect transistor);
the first front surface electrode is a source electrode, the first control electrode is a gate electrode, and the first back surface electrode is a drain electrode
(vertical MOSFET: source and gate on the front surface, drain on the back surface attached to the drain pattern; Figs. 5-9, 15-18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use SiC MISFETs as the first and second transistors of Rohm because Rohm expressly identifies SiC MOSFETs as suitable devices for the module.
Regarding claim 3, Rohm teaches the power module according to claim 1, as best understood, wherein
the first wiring pattern is connected to an output terminal
(pattern D4 connected to output terminal O; Figs. 5-9, 15-18);
the third wiring pattern is connected to a low-side terminal
(pattern S4 connected to negative-side / low-side power terminal N; Figs. 5-9, 15-18);
the second wiring pattern is connected to a high-side terminal
(pattern D1 connected to positive-side / high-side power terminal P; Figs. 5-9, 15-18; "high-terminal" in claim 3 is treated as a high-side terminal);
the fourth wiring pattern is connected to a source sense terminal
(pattern SSP4 connected to source-sense terminal SST4; Figs. 5-9, 15-18).
Regarding claim 4, Rohm teaches the power module according to claim 1, as best understood, wherein the fourth wiring pattern is disposed on the opposite side to the third wiring pattern so as to sandwich the first transistor in a plan view
(source-sense pattern SSP and source pattern S are disposed on opposite sides of transistor Q4 in plan view so that the transistor lies between the two patterns; Figs. 5-9, 15-18).
Regarding claim 5, Rohm teaches the power module according to claim 1, as best understood, wherein the fifth wiring pattern is connected to the first wiring pattern via a fourth wire
(source-signal / source-sense pattern of Q1 is connected into the source / output node associated with pattern D4 by wiring and/or a wire; Figs. 5-9, 15-18).
The mapping below is applied to claim 8 as best understood in view of the rejection under 35 U.S.C. § 112(b). In particular, "a fifth a first wiring pattern" is treated as a fifth wiring pattern, "a fourth wires" is treated as a fourth wire, and the fourth wiring pattern, which is not connected to either transistor in the claim body, is treated as a source-sense or gate pattern on the substrate.
Regarding independent claim 8, Rohm teaches a power module comprising:
an insulating layer on a surface of which wiring patterns are formed
(ceramic / insulating substrate having electrode patterns formed on a surface thereof; Abstract; Figs. 5-9, 15-18);
a first transistor having a first front surface electrode and a first control electrode on a front surface thereof and a first back surface electrode on a back surface thereof, the first back surface electrode being disposed on and electrically connected to a first wiring pattern
(Q4 or Q1; drain disposed on D4 or D1; source and gate connected by wires from the upper face of the die; Figs. 5-9, 15-18);
a second transistor having a second front surface electrode and a second control electrode on a front surface thereof and a second back surface electrode on a back surface thereof, the second back surface electrode being disposed on and electrically connected to a second wiring pattern
(the other of Q1 and Q4; drain disposed on the other of D1 and D4; source and gate connected by wires from the upper face of the die; Figs. 5-9, 15-18);
wherein the first front surface electrode is connected to a third wiring pattern via a plurality of first wires
(source connected to S4 by source wires SW; Figs. 5-9, 15-18);
the second front surface electrode is connected to the first wiring pattern via a plurality of third wires
(source of the other transistor connected to D4 by source wires SW; Figs. 5-9, 15-18);
and is connected to a fifth wiring pattern via a fourth wire
(source connected to SSP by source-sense wire SSW; Figs. 5-9, 15-18);
each of the first wiring pattern, the second wiring pattern, the third wiring pattern, the fourth wiring pattern and the fifth wiring pattern is connected to a corresponding external extraction terminal
(D4, D1, S4, SSP, and the remaining sense or gate pattern to terminals O, P, N, SST, and GT; Figs. 5-9, 15-18).
Rohm does not use the claim words "front surface electrode" and "back surface electrode." Rohm still teaches those electrodes, for the same reason set forth with respect to claim 1. The drain Rohm disposes on D1 or D4 is the back surface electrode. The source and gate Rohm connects by wires SW and SSW from the upper face of the die are the front surface electrode and the control electrode.
Rohm further teaches source-sense wiring on both Q1 and Q4 (SSP1 and SSP4), each brought out to a source-sense terminal. Mapping Q1 as the first transistor and Q4 as the second transistor, or the reverse, meets the wire assignments of claim 8 as best understood.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to read the Rohm half-bridge on claim 8 as mapped above. Rohm already discloses drain-down mounting of both devices and source-sense wires on both devices. The claim wording differs from Rohm's wording. The module Rohm discloses is the module claim 8 recites.
Regarding claim 9, Rohm teaches the power module according to claim 8, as best understood, wherein
the first transistor and the second transistor are composed of SiC MISFET, respectively
(SiC based MOSFET; description of Q1, Q4);
the second front surface electrode is a source electrode, the second control electrode is a gate electrode, and the second back surface electrode is a drain electrode
(vertical MOSFET construction; Figs. 5-9, 15-18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use SiC MISFETs as taught by Rohm for the reasons set forth with respect to claim 2.
Regarding claim 10, Rohm teaches the power module according to claim 8, as best understood, wherein
the first wiring pattern is connected to an output terminal
(pattern D4 / series node connected to output terminal O; Figs. 5-9, 15-18);
the third wiring pattern is connected to a low-side terminal
(source pattern connected to terminal N; Figs. 5-9, 15-18);
the second wiring pattern is connected to a high-side terminal
(drain pattern connected to terminal P; Figs. 5-9, 15-18);
the fifth wiring pattern is connected to a source sense terminal
(pattern SSP connected to source-sense terminal SST; Figs. 5-9, 15-18).
Regarding claim 11, Rohm teaches the power module according to claim 1, as best understood, wherein the fourth wiring pattern is disposed on the opposite side to the third wiring pattern so as to sandwich the first transistor in a plan view
(source-sense pattern and source pattern on opposite sides of the first transistor in plan view; Figs. 5-9, 15-18; "forth wiring pattern" is treated as the fourth wiring pattern).
Allowable Subject Matter
Claims 6, 7, 13, and 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art of record, taken alone or in combination, does not teach or fairly suggest, in combination with the other limitations of claim 1 as best understood, that an inductance of the second wire and the fourth wiring pattern is smaller than an inductance of the plurality of third wires, the first wiring pattern, the fourth wire and the fifth wiring pattern.
Rohm teaches separate source-sense wiring and source power wiring and discusses conductor length. Rohm does not teach the recited inductance comparison between (i) the second wire and the fourth wiring pattern and (ii) the plurality of third wires, the first wiring pattern, the fourth wire, and the fifth wiring pattern.
JP 2007-228711 A (IDS 07/15/2024) teaches a source-inductance relationship between a switching transistor and a synchronous-rectifier transistor. That reference does not teach the wiring-pattern inductance comparison of claim 6.
U.S. Patent Application Publication No. 2018/0159440 A1 (Xu) teaches common-source inductance in an inverter. Xu does not teach the wiring-pattern inductance comparison of claim 6.
Claim 6 also requires correction of antecedent basis for "the fourth wire," as set forth in the rejection under 35 U.S.C. 112(b).
Regarding claim 7, the prior art of record, taken alone or in combination, does not teach or fairly suggest, in combination with the other limitations of claim 1 as best understood, a sixth wiring pattern formed on the surface of the insulating layer, wherein a current tolerance of the plurality of third wires is greater than a current tolerance of a fifth wire that directly connects the sixth wiring pattern and the second control electrode.
Rohm teaches gate wiring patterns and gate wires. Rohm does not teach the recited current-tolerance comparison between the plurality of third wires and a fifth wire that directly connects a sixth wiring pattern and the second control electrode.
Regarding claim 13, the claim depends from claim 12. Upon correction of claim 12 to depend from claim 8, or another proper base claim, and upon correction of the indefiniteness of the base claim, claim 13 would be allowable for the same reason set forth with respect to claim 6: the prior art of record does not teach the recited inductance comparison.
Regarding claim 14, the prior art of record, taken alone or in combination, does not teach or fairly suggest, in combination with the other limitations of claim 8 as best understood, an eighth wiring pattern formed on the surface of the insulating layer, wherein a current tolerance of the plurality of first wires is greater than the current tolerance of a sixth wire that directly connects the eighth wiring pattern and the first control electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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16 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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