Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 18 is objected to because of the following informalities: "configured" should read "coupled". Appropriate correction is required. Claims 16-17 will be examined.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of copending Application No. 19/292,331 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because for claim 1 of the current application, they merely omit features that is recited in the claim 12 of patent/application such as wherein the first circuit is configured to in response to a first value of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in response to a second edge of the first clock signal, and the second value is different from the first value.
Claim 4 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of copending Application No. 19/292,331 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference claims limitation wherein the first circuit is configured to in response to a first value of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in response to a second edge of the first clock signal, the second value is different from the first value, and the first edge is half a clock cycle away from the second edge is identical in scope to the limitation wherein the first circuit is configured to in response to a first value of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in response to a second edge of the first clock signal, the second value is different from the first value, and the first edge is half a clock cycle away from the second edge in the instance application.
Regarding claims 1 and 4, see table below.
Current Application 18/772,677
Reference Application 19/292,331
1. (Original) An integrated circuit (IC) device, comprising: a first semiconductor die, comprising: a first transmitting circuit configured to transmit an output clock signal corresponding to a first clock signal; a first receiving circuit configured to receive an input clock signal and an input signal, and output, based on the input clock signal, a first signal corresponding to the input signal; and a first circuit configured to output, based on the first clock signal, a second signal corresponding to the first signal; and a second semiconductor die, comprising: a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal; and a second transmitting circuit coupled to the first receiving circuit, and configured to transmit, based on the output clock signal, the input signal to the first receiving circuit, and transmit the input clock signal corresponding to the output clock signal to the first receiving circuit.
4. (Original) The IC device of claim 1, wherein the first circuit is configured to in response to a first value of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in response to a second edge of the first clock signal, the second value is different from the first value, and the first edge is half a clock cycle away from the second edge.
1. An integrated circuit (IC) device, comprising: a first semiconductor die, comprising: a first transmitting circuit configured to transmit an output clock signal corresponding to a first clock signal; a first receiving circuit configured to receive an input clock signal and an input signal, and output, based on the input clock signal, a first signal corresponding to the input signal; and a first circuit configured to output, based on the first clock signal, a second signal corresponding to the first signal, of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in wherein the first circuit is configured to in response to a first value response to a second edge of the first clock signal, and the second value is different from the first value.
12. The IC device of claim 1, further comprising: a second semiconductor die, comprising: a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal; and a second transmitting circuit coupled to the first receiving circuit, and configured to transmit, based on the output clock signal, the input signal to the first receiving circuit, and transmit the input clock signal corresponding to the output clock signal to the first receiving circuit.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 21 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 12 of copending Application No. 19/292,331 in view of Morgan (GB-2572463-A and Morgan hereinafter.). Regarding claim 21, see table below.
Current Application 18/772,677
Reference Application 19/292,331
21. (Previously Presented) An integrated circuit (IC) device, comprising: a first semiconductor die, comprising: a first transmitting circuit configured to transmit an output signal and an output clock signal associated with the output signal; and a first receiving circuit configured to receive an input signal and an input clock signal associated with the input signal; and a second semiconductor die, comprising: a second receiving circuit coupled to the first transmitting circuit to receive the output signal and the output clock signal; a circuit coupled to the second receiving circuit to receive the output clock signal, and configured to output the input clock signal corresponding to the output clock signal, wherein the input clock signal has a phase lead relative to the output clock signal; and a second transmitting circuit coupled to the circuit and the first receiving circuit, and configured to transmit, to the first receiving circuit and based on the output clock signal, the input signal and the input clock signal.
1. An integrated circuit (IC) device, comprising: a first semiconductor die, comprising: a first transmitting circuit configured to transmit an output clock signal corresponding to a first clock signal; a first receiving circuit configured to receive an input clock signal and an input signal, and output, based on the input clock signal, a first signal corresponding to the input signal; and a first circuit configured to output, based on the first clock signal, a second signal corresponding to the first signal, wherein the first circuit is configured to in response to a first value of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in response to a second edge of the first clock signal, and the second value is different from the first value.
12. The IC device of claim 1, further comprising: a second semiconductor die, comprising: a second receiving circuit coupled to the first transmitting circuit to receive the output clock signal; and a second transmitting circuit coupled to the first receiving circuit, and configured to transmit, based on the output clock signal, the input signal to the first receiving circuit, and transmit the input clock signal corresponding to the output clock signal to the first receiving circuit.
Regarding claim 21, 19/292,331 fails to disclose wherein the circuit is configured to output the input clock signal corresponding to the output clock signal, wherein the input clock signal has a phase lead relative to the output clock signal; and a second transmitting circuit coupled to the circuit and the first receiving circuit.
However, Morgan in the same field of endeavor discloses the circuit [234 accepting output of 232] configured to output the input clock signal [SYNCB from 236 and 220] corresponding to the output clock signal [pg. 9-10], wherein the input clock signal has a phase lead relative to the output clock signal [fig. 2 showing FCKA-5 showing second high level after a first high level of DCLKA with pg. 8 of Morgan disclosing “It will be assumed that the signal SYNCA is the same as the signal FLCKA-5”]; and a second transmitting circuit [220 and 250] coupled to the circuit [220 and 250 coupled to 234] and the first receiving circuit [220 and 250 coupled to 132 and 150], and configured to transmit, to the first receiving circuit [132 and 150] and based on the output clock signal [pg. 9-10, SYNCA], the input signal [DATA from 250 ] and the input clock signal [SYNCB].
Claim 21 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 12 of copending Application No. 19/292,331 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claim 21 of the current application merely omit features that is recited in the claim 1 of Application No. 19/292,331 such as a first circuit configured to output, based on the first clock signal, a second signal corresponding to the first signal, wherein the first circuit is configured to in response to a first value of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in response to a second edge of the first clock signal, and the second value is different from the first value.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morgan et al. (GB 2572463 A and Morgan hereinafter.)
Regarding claim 21, Morgan discloses [fig. 1] an integrated circuit (IC) device, comprising: a first semiconductor die [domain A], comprising: a first transmitting circuit [120 and 150] configured to transmit an output signal [DATA] and an output clock signal [SYNCA] associated with the output signal [SYNCA associated with DATA from 150 via FCLKA signal, pg. 9-10]; and[132 and 150] configured to receive an input signal [DATA from 250] and an input clock signal [SYNCB from 220] associated with the input signal [SYNCB associated with DATA from 250 via FCLKAB, pg. 9-10]; and a second semiconductor die [domain B], comprising: a second receiving circuit [232 and 250] coupled to the first transmitting circuit to receive the output signal [250 accepting DATA from 150] and the output clock signal [232 accepting SYNCA from 120]; a circuit [234 accepting output of 232] coupled to the second receiving circuit [232 and 250] to receive the output clock signal [pg. 13 of Morgan disclosing “the synchronisation signal SYNCA is received by the retiming unit 232 and retimed to be synchronous to the domain clock signal DCLKB to produce the retimed equivalent signal SYNCA(R).”], and configured to output the input clock signal [SYNCB from 236 and 220] corresponding to the output clock signal [pg. 9-10], wherein the input clock signal has a phase lead relative to the output clock signal [fig. 2 showing FCKA-5 showing second high level after a first high level of DCLKA with pg. 8 of Morgan disclosing “It will be assumed that the signal SYNCA is the same as the signal FLCKA-5”]; and a second transmitting circuit [220 and 250] coupled to the circuit [220 and 250 coupled to 234] and the first receiving circuit [220 and 250 coupled to 132 and 150], and configured to transmit, to the first receiving circuit [132 and 150] and based on the output clock signal [pg. 9-10, SYNCA], the input signal [DATA from 250 ] and the input clock signal [SYNCB].
Regarding claim 23, wherein the circuit [234 accepting output of 232] comprises: an input coupled to an output of the second receiving circuit [232 and 250] to receive the output clock signal [pg. 13 of Morgan disclosing “the synchronisation signal SYNCA is received by the retiming unit 232 and retimed to be synchronous to the domain clock signal DCLKB to produce the retimed equivalent signal SYNCA(R).”], and an output at which the circuit is configured to output the input clock signal [SYNCB from 220] corresponding to the output clock signal [SYNCA, pg. 9-10] and having the phase lead relative to the output clock signal [fig. 2 showing FCKA-5 showing second high level after a first high level of DCLKA with pg. 8 of Morgan disclosing “It will be assumed that the signal SYNCA is the same as the signal FLCKA-5”], and the second transmitting circuit [220 and 250] has an input coupled to the output of the circuit to receive the input
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Morgan in view of Nakai et al. (US 20230206985 A1 and Nakai hereinafter.).
Regarding claim 1, Morgan discloses [fig. 1] An integrated circuit (IC) device, comprising: a first semiconductor die [domain A], comprising: a first transmitting circuit [120 and 150] configured to transmit an output clock signal [SYNCA] corresponding to a first clock signal [110]; a first receiving circuit [132 and 150] configured to receive an input clock signal [SYNCB from 220] and an input signal [DATA from 250], and output, based on the input clock signal [output of 132 into 130 and into 120], a first signal [FCLKA] a first circuit [134] configured to output, based on the first clock signal [SYNCA based on 110] a second signal [output of 134] corresponding to the first signal [output of 134 corresponding to FCLKA and SYNCA]; and a second semiconductor die [domain B], comprising: a second receiving circuit [232 and 250] coupled to the first transmitting circuit to receive the output clock signal [232 accepting SYNCA from 120]; and a second transmitting circuit [220 and 250] coupled to the first receiving circuit, and configured to transmit, based on the output clock signal [232/234/236 accepting SYNCA from 120], the input signal [DATA out of 250 into 150 based on FCLKB from 220] to the first receiving circuit [150 accepting data from 250], and transmit the input clock signal [output of 132 into 130 and into 120] corresponding to the output clock signal [SYNCA] to the first receiving circuit.
Morgan does not explicitly disclose the first receiving circuit outputting the first signal corresponding to the input signal.
However, Nakai discloses the first receiving circuit [fig. 4, core die of 404] outputting the first signal [delay code 2 output from 490] corresponding to the input signal [delay code 2 corresponding to output of 424, wherein output of 424 corresponds with data and clock information via inputs from 438 and 439].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the first receiving circuit as taught by Morgan to output the first signal corresponding to the input signal as taught by Nakai to improve data alignment in a communication system.
Regarding claim 2, Morgan in view of Nakai discloses further wherein the first transmitting circuit [Morgan, 120 and 150] is further configured to transmit, based on the first clock signal [Morgan, 110], an output signal [Morgan, SYNCA], the second receiving circuit [Morgan, 232 and 250] is further configured to receive the output signal from the first transmitting circuit [as shown in fig. 1], and the second transmitting circuit is configured to transmit the input signal responsive to the output signal [Morgan, 232 transmitting SYNCA(R) to 234].
Regarding claim 10, Morgan in view of Nakai discloses further wherein the second semiconductor die [Morgan, fig. 1, domain B] further comprises a second circuit coupled to the second receiving circuit [Morgan, 234 accepting output of 232] to receive the output clock signal [pg. 13 of Morgan disclosing “the synchronization signal SYNCA is received by the retiming unit 232 and retimed to be synchronous to the domain clock signal DCLKB to produce the retimed equivalent signal SYNCA(R).”], and the second circuit is configured to output the input clock signal corresponding to the output clock signal [234, 236 and 220 output FCLKB onto 250], wherein the input clock signal has a phase lead relative to the output clock signal [fig. 2 showing FCKA-5 showing second high level after a first high level of DCLKA with pg. 8 of Morgan disclosing “It will be assumed that the signal SYNCA is the same as the signal FLCKA-5”].
Claim(s) 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Morgan in view of Nakai further in view of Rombach et al. (US 7800975 and Rombach hereinafter.).
Regarding claim 11, Morgan in view of Nakai discloses all the features regarding claim 1 as indicated above. Morgan in view of Nakai does not explicitly disclose wherein the second semiconductor die further comprises a phase locked loop (PLL) comprising: a reference input coupled to the second receiving circuit to receive the output clock signal, a feedback input, an output at which the PLL is configured to output the input clock signal corresponding to the output clock signal, and a feedback path coupled between the output and the feedback input, the feedback path comprising a delay circuit.
However, Rombach [fig. 1] discloses wherein the second semiconductor die further comprises a phase locked loop (PLL) [PLL AND PHASE ALIGNER] comprising: a reference input coupled to the second receiving circuit to receive the output clock signal [fig. 1, CLK input on BUF1], a feedback input [feedback inputs on BUF2], an output at which the PLL is configured to output the input clock signal corresponding to the output clock signal [PLL_CLK and PLL_FB], and a feedback path coupled between the output and the feedback input [PLL_FB through DEL1, BUF3 and back into BUF2], the feedback path comprising a delay circuit [DEL1].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Morgan to include the phase locked loop and associated circuitry as taught by Rombach to improve data alignment performance in an integrated circuit.
Regarding claim 12, Morgan in view of Nakai further in view of Rombach discloses all the features regarding claim 11 as indicated above. Morgan in view of Nakai further in view of Rombach does not explicitly disclose wherein a time delay of the delay circuit corresponds to a sum of a first time delay and a second time delay, the first time delay is between a master clock signal of the first semiconductor die, the master clock signal corresponding to the first clock signal, and the output clock signal at an output of the second receiving circuit, and the second time delay is between the output clock signal at the output of the second receiving circuit, and the input clock signal at an output of the first receiving circuit.
However, to ensure proper communication between dies, any delay elements within the phase locked loop of Rombach would have to be in sync with CLK GEN A and therefore the synchronization signals SYNCA and SYNB. Without this feature, the delay element would glitch and errors would form at the output of the phase locked loop. Therefore, it would have been obvious to one of ordinary skill in the art to have the delay element disclose by Romback to be in sync with the first clock signals and the output and input clock signals to ensure proper operations of the entire system. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Claim(s) 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Morgan in view of Nakai further in view of Rombach further in view of Loyer et al. (US 6624681 and Loyer hereinafter.).
Regarding claim 13, Morgan in view of Nakai further in view of Rombach discloses all the features regarding claim 11 as indicated above. Morgan in view of Nakai further in view of Rombach does not explicitly disclose wherein the second semiconductor die further comprises a clock tree coupled between the output of the PLL and the delay circuit.
However, Loyer discloses a clock tree coupled between the output of the PLL and the delay circuit [fig. 2 and 3, clock gating circuit 128 having delay feedback delay circuit 290 outputting gated PLL to clock tree 125 with clock tree 125 outputting buffered PLL outputs as shown in fig. 2].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the IC device as taught by Morgan in view of Rombach to include the clock tree as taught by Loyer to reduce power consumption by stopping the clock generation during idle state
Regarding claim 14, Morgan in view of Nakai further in view of Rombach further in view of Loyer discloses all the features regarding claim 13 as indicated above. Morgan in view of Nakai further in view of Rombach further in view of Loyer does not explicitly disclose wherein the first semiconductor die comprises a plurality of first clock I/O circuits, each comprising: a first clock input buffer, and a first clock output buffer, the second semiconductor die comprises a plurality of second clock I/O circuits, each comprising: a second clock input buffer coupled to the first clock output buffer of a corresponding first clock I/O circuit among the plurality of first clock I/O circuits, and a second clock output buffer coupled to the first clock input buffer of the corresponding first clock I/O circuit, the second receiving circuit comprises the second clock input buffer of one second clock I/O circuit among the plurality of second clock I/O circuits, and the second transmitting circuit comprises the second clock output buffer of said one second clock I/O circuit.
However, Morgan discloses in fig. 1 GCLK providing common global clock signal GCLK to and output respective domain clock signals DLKCA and DCLKB with pg. 7 disclosing “The clock generators 110 and 210 operate generally in the same way as one another, in that they receive a common global clock signal GCLK and output respective domain clock signals DCLKA and DCLKB. The clock generators 110 and 210 may however differ from one another in some respects, for example in terms of their precision/accuracy. Thus, it may be that on average the frequencies of the domain clock signals DCLKA and DCLKB are the same as one another, or have some defined relationship to one another, but that over time the relationship fluctuates.”.
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date to provide a common synchronization clocking feature-set using clock I/O circuits, as taught by Morgan in order to provide a common clocking structure between circuit dies thereby improving system performance. Since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Claim(s) 18 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Morgan in view of Rombach.
Regarding claim 18, Morgan discloses an integrated circuit (IC) device [fig. 1], comprising: a clock input buffer [clock generators 110 and 210], comprising: an input configured to be coupled to a die-to-die (D2D) interface structure [GCLK providing clocking information to domain A and domain B via 110 and 210], and an output [output of 110 and 210].
Morgan does not explicitly disclose a phase locked loop (PLL), comprising: a reference input coupled to the output of the clock input buffer, a feedback input, an output, and a feedback path coupled between the feedback input and the output of the PLL, the feedback path comprising a delay circuit; a clock output buffer, comprising: an input coupled to the output of the PLL, and an output configured to be coupled to a further D2D interface structure; and further comprising: a multiplexer, comprising: a first input coupled to the reference input of the PLL, a second input configured to the output of the PLL, a selection input configured to receive a selection signal, and an output coupled to the input of the clock output buffer.
However, Rombach discloses [fig. 1] a phase locked loop (PLL)[PLL AND PHASE ALIGNER], comprising: a reference input coupled to the output of the clock input buffer [fig. 1, CLK input on BUF1], a feedback input [feedback inputs on BUF2], an output [PLL_CA_CNTRL, PLL_CLK and PLL_FB], and a feedback path coupled between the feedback input and the output of the PLL [PLL_FB through DEL1, BUF3 and back into BUF2], the feedback path comprising a delay circuit [DEL1]; a clock output buffer [BUF4], comprising: an input coupled to the output of the PLL [through DEL2], and an output configured to be coupled to a further D2D interface structure [fig. 3, CLK providing clocking information to SDRAM1 and SDRAM2]; and further comprising: a multiplexer [MUX], comprising: a first input coupled to the reference input of the PLL [first input of MUX coupled to BUF1 through DIV], a second input configured to the output of the PLL [CA/CNTRL provided input from PLL_CA_CNTRL through flip flop FF1], a selection input configured to receive a selection signal [LEARN CYCLE], and an output coupled to the input of the clock output buffer [output of MUX providing output signal to FF1, FF2, EXOR gate and FF4].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Morgan to include the phase locked loop and associated circuitry as taught by Rombach to improve data alignment performance in an integrated circuit.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Morgan in view of Rombach further in view of Loyer.
Regarding claim 24, Morgan in view of Rombach discloses all the features regarding claim 18 as indicated above. Morgan in view of Rombach does not explicitly disclose a clock tree coupled between the output of the PLL and the delay circuit.
However, Loyer discloses a clock tree coupled between the output of the PLL and the delay circuit [fig. 2 and 3, clock gating circuit 128 having delay feedback delay circuit 290 outputting gated PLL to clock tree 125 with clock tree 125 outputting buffered PLL outputs as shown in fig. 2].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the IC device as taught by Morgan in view of Rombach to include the clock tree as taught by Loyer to reduce power consumption by stopping the clock generation during idle state
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Morgan in view of Loyer.
Regarding claim 22, Morgan discloses all the features regarding claim 21 as indicated above. Morgan does not explicitly disclose wherein the circuit of the second semiconductor die comprises a phase locked loop (PLL) comprising: a reference input coupled to the second receiving circuit to receive the output clock signal, a feedback input, an output at which the PLL is configured to output the input clock signal corresponding to the output clock signal, and a feedback path coupled between the output and the feedback input, the feedback path comprising a delay circuit.
However, Loyer discloses [fig. 1] wherein the circuit of the second semiconductor die comprises a phase locked loop (PLL)[PLL AND PHASE ALIGNER] comprising: a reference input coupled to the second receiving circuit to receive the output clock signal [fig. 1, BUF1 receiving CLK input], a feedback input [feedback inputs on BUF2], an output at which the PLL is configured to output the input clock signal corresponding to the output clock signal [PLL_CLK providing output clocking signal], and a feedback path coupled between the output and the feedback input [EXTERNAL FEEDACK coupling feedback input with feedback output], the feedback path comprising a delay circuit [DEL1].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the teachings of Morgan to include the phase locked loop and associated circuitry as taught by Rombach to improve data alignment performance in an integrated circuit.
Allowable Subject Matter
Claims 3-9 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, Morgan in view of Nakai does not disclose “wherein the first circuit is configured to in response to a first value of a first selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the first selection signal, output the second signal in response to a second edge of the first clock signal, the second value is different from the first value, the first edge is one of a rising edge and a falling edge of the first clock signal, and the second edge is the other of the rising edge and the falling edge of the first clock signal.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Morgan in view of Nakai to incorporate these missing features.
Regarding claim 4, Morgan in view of Nakai does not disclose “wherein the first circuit is configured to in response to a first value of a selection signal, output the second signal in response to a first edge of the first clock signal, and in response to a second value of the selection signal, output the second signal in response to a second edge of the first clock signal, the second value is different from the first value, and the first edge is half a clock cycle away from the second edge.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Morgan in view of Nakai to incorporate these missing features.
Regarding claim 5, Morgan in view of Nakai does not disclose “wherein the first circuit comprises: a flip-flop, comprising: an input coupled to the first receiving circuit to receive the first signal, an output at which the flip-flop is configured to output the second signal, and a clock input, and a multiplexer, comprising: a non-inverting input configured to receive the first clock signal, an inverting input configured to receive the first clock signal, a selection input configured to receive a selection signal, and an output coupled to the clock input of the flip-flop.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Morgan in view of Nakai to incorporate these missing features.
Regarding claim 6, Morgan in view of Nakai does not disclose “wherein the first circuit further comprises a storage circuit having an output coupled to the selection input of the multiplexer, and the storage circuit storing a predetermined value of the selection signal, the predetermined value corresponding to either the multiplexer configured to output the first clock signal received at the non- inverting input to the clock input of the flip-flop, or the multiplexer configured to output the first clock signal received at the inverting input to the clock input of the flip-flop.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Morgan in view of Nakai to incorporate these missing features.
Regarding claim 7, Morgan in view of Nakai does not disclose “wherein the first transmitting circuit is further configured to transmit, based on the first clock signal, an output signal corresponding to a test signal, the second receiving circuit is further configured to receive the output signal from the first transmitting circuit, and provide the output signal to the second transmitting circuit, the second transmitting circuit is configured to transmit the input signal corresponding to the output signal, and the first semiconductor die further comprises a control circuit configured to select one edge of a rising edge and a falling edge of the first clock signal, based on a comparison of first data in the test signal and second data in the second signal, and control the first circuit to output the second signal in response to the selected edge of the first clock signal.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Morgan in view of Nakai to incorporate these missing features.
Regarding claim 8, Morgan in view of Nakai does not disclose “wherein the first circuit comprises: a flip-flop, comprising: an input coupled to the first receiving circuit to receive the first signal, an output at which the flip-flop is configured to output the second signal, and a clock input, and a multiplexer, comprising: a non-inverting input configured to receive the first clock signal, an inverting input configured to receive the first clock signal, a selection input coupled to an output of the control circuit to receive a selection signal corresponding to the selected edge, and an output coupled to the clock input of the flip-flop.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Morgan in view of Nakai to incorporate these missing features.
Regarding claim 9, Morgan in view of Nakai does not disclose “wherein the second semiconductor die further comprises a multiplexer, the multiplexer comprising: a first input configured to receive the output clock signal, a second input configured to receive to a second clock signal of the second semiconductor die, the second clock signal independent from the first clock signal of the first semiconductor die, a selection input configured to receive a selection signal, and an output coupled to the second transmitting circuit.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Morgan in view of Nakai to incorporate these missing features.
Regarding claim 15, Morgan in view of Nakai further in view of Rombach does not disclose “wherein the second semiconductor die further comprises a multiplexer, the multiplexer comprising: a first input coupled to the reference input of the PLL to receive the output clock signal, a second input configured to the output of the PLL, a selection input configured to receive a selection signal, and an output coupled to the second transmitting circuit.”. Furthermore, it would not be obvious to one of ordinary skill in the art to modify the teachings of Nakai further in view of Rombach to incorporate these missing features.
Conclusion
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/JAMES G YEAMAN/ Examiner, Art Unit 2836
/TAELOR KIM/ Supervisory Patent Examiner, Art Unit 2836
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