Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of elected species in the reply filed on 11/24/2025 is acknowledged. The traversal is on the ground(s) is found persuasive.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ferris et al. (US 20130195235 A1 and Ferris hereinafter.).
Regarding claim 1, Ferris discloses an integrated circuit (IC) device [fig. 1 and 2], comprising: a first semiconductor die [2], comprising: a first transmitting circuit [top half of 2] configured to transmit an output clock signal [CK into 28] corresponding to a first clock signal [clk_pll]; a first receiving circuit [bottom half of 2] configured to receive an input clock signal [CK onto 28a] and an input signal [DATA on 28a], and output, based on the input clock signal, a first signal [12a into 30a] corresponding to the input signal [para. 38]; and a first circuit [24] configured to output, based on the first clock signal, a second signal corresponding to the first signal [para. 56, output of 24 into 54]; and a second semiconductor die [4], comprising: a second receiving circuit [top half of 4] coupled to the first transmitting circuit to receive the output clock signal [as shown]; and a second transmitting circuit [bottom half of 4] coupled to the first receiving circuit, and configured to transmit, based on the output clock signal, the input signal to the first receiving circuit [DATA signal from bottom half of 4 and into bottom half of 2], and transmit the input clock signal corresponding to the output clock signal to the first receiving circuit [CK from bottom half of 4 into 28a of bottom half of 2].
Regarding claim 19, Ferris discloses [fig. 1 and 2] a method, comprising: transmitting, to a semiconductor die [4], an output signal [data from 2] and an output clock signal [CK from 2] associated with the output signal [fig. 2, CK and data stream driven by common clock signal from 8]; receiving, from the semiconductor die, an input signal [DATA from 4 into 2] and an input clock signal [CK from 4 into 2] associated with the input signal [both dies driven by XTAL], the input signal corresponding to the output signal [as shown], the input clock signal corresponding to the output clock signal [both dies driven by XTAL]; based on a comparison of data in the output signal with data obtained from the input signal, selecting a clock signal [fig. 3, via 68]; and based on the selected clock signal, obtaining further data from further input signals received from the semiconductor die [data from 82 and 83].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ferris in view of Liang et al. (TW I810962 B and Liang hereinafter.).
Regarding claim 2, Ferris discloses all the features regarding claim 1 as indicated above. Ferris discloses further wherein the first transmitting circuit [top half of 2] is further configured to transmit, based on the first clock signal [clk_pll], an output signal [DATA onto 28], the second receiving circuit[top half of 4] is further configured to receive the output signal from the first transmitting circuit [as shown]. Ferris does not explicitly disclose the second transmitting circuit is configured to transmit the input signal responsive to the output signal.
However, Liang discloses the second transmitting circuit [10] is configured to transmit the input signal [out of 521] responsive to the output signal [pg. 8 regarding synchronization between 10 and 20]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Ferris to include the second transmitting circuit is configured to transmit the input signal responsive to the output signal as taught by Liang to improve communication performance between interconnected chips.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ferris in view of Kawasaki et al. (US 7298188 and Kawasaki hereinafter.).
Regarding claim 16, Ferris discloses [fig. 1 and 2] an integrated circuit (IC) device, comprising: a clock input buffer [28], comprising: an input configured to be coupled to a die-to-die (D2D) interface structure [4 coupled to 2], and an output [output of 28 into 30]; a phase locked loop (PLL) [11a]. Ferris does not explicitly disclose the PLL comprising: a reference input coupled to the output of the clock input buffer, a feedback input, an output, and a feedback path coupled between the feedback input and the output of the PLL, the feedback path comprising a delay circuit; and a clock output buffer, comprising: an input coupled to the output of the PLL, and an output configured to be coupled to a further D2D interface structure.
However, Kawasaki discloses the PLL [fig. 2, PLL 22] comprising: a reference input [ck0] coupled to the output of the clock input buffer [21], a feedback input [ckf], an output [ckr], and a feedback path [24] coupled between the feedback input and the output of the PLL [as shown], the feedback path comprising a delay circuit [24]; and a clock output buffer [23 comprising a plurality of buffers], comprising: an input coupled to the output of the PLL [as shown], and an output configured to be coupled to a further D2D interface structure [20 used in plurality interconnected chips as shown in fig. 1]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Ferris to include the PLL comprising: a reference input coupled to the output of the clock input buffer, a feedback input, an output, and a feedback path coupled between the feedback input and the output of the PLL, the feedback path comprising a delay circuit; and a clock output buffer, comprising: an input coupled to the output of the PLL, and an output configured to be coupled to a further D2D interface structure as taught by Kawasaki to improve reliability within data input/output operations.
Regarding claim 17, Ferris in view of Kawasaki discloses further comprising: a clock tree coupled between the output of the PLL and the delay circuit [Kawasaki, as shown in fig. 2].
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Ferris in view of Snoeij et al. (US 20180191366 A1 and Snoeij hereinafter.) further in view of Wang et al. (TW I741960 B and Wang hereinafter.).
Regarding claim 21, Ferris discloses an integrated circuit (IC) device [fig. 1 and 2], comprising: a first semiconductor die [2], comprising: a first transmitting circuit [top half of 2] configured to transmit an output signal [data onto 28] and an output clock signal [CK onto 28] associated with the output signal [fig. 2, signals out of 6 (AKA TX PHY of fig. 1 clocked by 8]; and a first receiving circuit [bottom half of 2] configured to receive an input signal [DATA on 28a] and an input clock signal [CK onto 28a] associated with the input signal [fig. 2, signals out of 6 (AKA TX PHY of fig. 1 clocked by 8]; and a second semiconductor die [4], comprising: a second receiving circuit [top half of 4] coupled to the first transmitting circuit to receive the output signal and the output clock signal [as shown]; a circuit [28] coupled to the second receiving circuit to receive the output clock signal [as shown] coupled to the circuit [through 9 and associated unlabeled circuitry coupling top half of 4 with bottom half of 28] and the first receiving circuit [28 coupled to 24 through 12 and 14]. Ferris does not explicitly disclose the circuit is configured to output the input clock signal corresponding to the output clock signal, wherein the input clock signal has a phase lead relative to the output clock signal; and the second transmitting circuit is configured to transmit, to the first receiving circuit and based on the output clock signal, the input signal and the input clock signal.
However, Snoeij discloses the circuit [154] is configured to output [on 168] the input clock signal corresponding to the output clock signal [output of 124]; and the second transmitting circuit [circuitry associated with 124 of 106] is configured to transmit, to the first receiving circuit [circuitry associated with 154 of 108] and based on the output clock signal, the input signal and the input clock signal [fig. 3, method 300]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Ferris to include the circuit is configured to output the input clock signal corresponding to the output clock signal; and the second transmitting circuit is configured to transmit, to the first receiving circuit and based on the output clock signal, the input signal and the input clock signal as taught by Snoeij to improve mitigating of noise and aliasing problems in a circuit. Ferris in view of Snoeij does not explicitly disclose the input clock signal has a phase lead relative to the output clock signal.
However, Wang discloses the input clock signal has a phase lead relative to the output clock signal [pg. 6-7]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Ferris in view of Snoeij to include the input clock signal has a phase lead relative to the output clock signal as taught by Wang to improve functionality with higher performance in a circuit.
Allowable Subject Matter
Claims 3-5, 7, 9-11, 18, 20 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JAMES G YEAMAN/Examiner, Art Unit 2842 /LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842