DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-13 and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Juang et al. (U.S. Patent 8,269,539) in view of Culler (U.S. Patent 6,906,567).
Claim 1: Li teaches a circuit (Figure 3), comprising:
one or more de-skew stages (301-303);
wherein each of the one or more de-skew stages is configured to adjust a transition edge of a signal (column 7 lines 3-10 and 45-57) and includes:
a single inverter (313, 323);
a header (311, 312) configured to couple a first supply voltage (VDD) to the single inverter; and
a footer (321, 322) configured to couple a second supply voltage (ground) to the single inverter.
Li does not specifically teach a capacitor coupled to the output of the single inverter.
Juang teaches a capacitor (24; Figure 2) coupled to the output of the single inverter (Sw1, Sw2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the capacitor taught by Juang in the circuit of Li to further calibrate the slew rate of the driving voltage (column 4 lines 65-67 and column 5 lines 1-2).
Juang further teaches that the capacitor is adjustable (column 4 lines 65-66). Li and Juang do not specifically teach a switch circuit coupled between the output of the single inverter and the capacitor.
Culler teaches a switch circuit (225, 235, 245; Figure 2) coupled between the output of the single inverter (215 corresponding to outp of Li) and the capacitor (220, 230, 240 corresponding to the adjustable capacitance 24 of Juang).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the switch circuit taught by Culler in the circuit of Li and Juang to further control the slew rate using capacitive elements (column 3 lines 10-15).
Claim 2: The combined circuit further teaches N p-type metal-oxide-semiconductor (PMOS) transistors (311, 312; Figure 3 of Li where N=2) and the footer includes N n-type metal-oxide-semiconductor (NMOS) transistors (322, 323; Figure 3 of Li).
Claim 3: The combined circuit further teaches that the single inverter is configured to alternately couple with the first supply voltage from the N PMOS transistors and the second supply voltage from the N NMOS transistors (to VDD and ground via Vpres, Vpcorner, Vnres and Vncorner when either 313 or 323 are on; Figure 3 of Li).
Claim 4: The combined circuit further teaches that N corresponds to an adjustment range of the transition edge of the signal (column 7 lines 3-10 of Li).
Claim 7: The combined circuit further teaches that the one or more de-skew stages are included in a transmitter (Figures 1 and 2 of Li) and operatively coupled between a clock tree (column 6 lines 20-36 of Li) and a serializer (105; Figure 1 of Li).
Claim 8: The combined circuit further teaches that the one or more de-skew stages are included in a receiver (Figures 1 and 2 and column 6 lines 20-36 of Li) and operatively coupled between a data lane (output of 105 of Li) and de-serializer (135 of Li).
Claim 9: The combined circuit further teaches that the one or more de-skew stages are included in a corresponding one of a plurality of data lanes operatively interposed between a transmitter and a receiver (120, 215; Figures 1 and 2 of Li).
Claim 10: The combined circuit further teaches that the header includes N p-type metal-oxide-semiconductor (PMOS) transistors (311, 312; Figure 3 of Li where N=2), a first current source (409; Figure 4 of Li that generates Vpcorner), N first switches (402 of Li for each slice 301-303) each selectively configured to couple the first supply voltage to a corresponding one of the PMOS transistors (to Vpcorner), and N second switches (407 of Li for each slice 301-303) each configured to selectively couple the first current source to a corresponding one of the PMOS transistors (via Vpcorner); and
wherein the footer include N n-type metal-oxide-semiconductor (NMOS) transistors (322, 323) and a second current source (509; Figure 5 of Li providing Vncorner), N third switches (502 for each slice 301-303) each configured to selectively couple the second supply voltage to a corresponding one of the NMOS transistors (via Vncorner), and N fourth switches (507 for each slice 301-303) each configured to selectively couple the second current source to a corresponding one of the NMOS transistors (via Vncorner).
Claim 11: Li teaches a circuit (Figure 3), comprising:
one or more de-skew stages (301-303) included in a data lane (120 and 215; Figures 1 and 2) of at least one of a transmitter or a receiver (110; Figure 1);
wherein each of the one or more de-skew stages includes:
an inverter (313, 323) having an input (inp) and an output (outp), wherein the input is configured to receive a signal (signal at inp) and the output is configured to provide an updated version of the signal with an adjusted transition edge (column 7 lines 3-10 and 45-57);
a header (311, 312) configured to couple a first supply voltage (VDD) to the single inverter; and
a footer (321, 322) configured to couple a second supply voltage (ground) to the single inverter.
Li does not specifically teach a capacitor coupled to the output of the single inverter.
Juang teaches a capacitor (24; Figure 2) coupled to the output of the single inverter (Sw1, Sw2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the capacitor taught by Juang in the circuit of Li to further calibrate the slew rate of the driving voltage (column 4 lines 65-67 and column 5 lines 1-2).
Juang further teaches that the capacitor is adjustable (column 4 lines 65-66). Li and Juang do not specifically teach a switch circuit coupled between the output of the single inverter and the capacitor.
Culler teaches a switch circuit (225, 235, 245; Figure 2) coupled between the output of the single inverter (215 corresponding to outp of Li) and the capacitor (220, 230, 240 corresponding to the adjustable capacitance 24 of Juang).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the switch circuit taught by Culler in the circuit of Li and Juang to further control the slew rate using capacitive elements (column 3 lines 10-15).
Claim 12: The combined circuit further teaches N p-type metal-oxide-semiconductor (PMOS) transistors (311, 312; Figure 3 of Li where N=2) and the footer includes N n-type metal-oxide-semiconductor (NMOS) transistors (322, 323; Figure 3 of Li) and the inverter is configured to alternately couple with the first supply voltage from the N PMOS transistors and the second supply voltage from the N NMOS transistors (to VDD and ground via Vpres, Vpcorner, Vnres and Vncorner when either 313 or 323 are on; Figure 3 of Li).
Claim 13: The combined circuit further teaches that N corresponds to an adjustment range of the transition edge of the signal (column 7 lines 3-10 of Li).
Claim 15: The combined circuit further teaches that the one or more de-skew stages are included in a transmitter (Figures 1 and 2 of Li) and operatively coupled between a clock tree (column 6 lines 20-36 of Li) and a serializer (105; Figure 1 of Li).
Claim 16: The combined circuit further teaches that the one or more de-skew stages are included in a receiver (Figures 1 and 2 and column 6 lines 20-36 of Li) and operatively coupled between a data lane (output of 105 of Li) and de-serializer (135 of Li).
Claim 17: The combined circuit further teaches that the one or more de-skew stages are included in a corresponding one of a plurality of data lanes operatively interposed between a transmitter and a receiver (120, 215; Figures 1 and 2 of Li).
Claim 18: Li teaches a method for operating one or more de-skew stages (301-303; Figure 3) included in a data lane of at least one of a transmitter or a receiver (Figures 1 and 2), the method comprising:
receiving, by an input of an inverter (313, 323), a signal (at inp);
selectively, based at least in part on the signal (via 311, 312 and 313), coupling a first supply voltage (VDD) to the inverter;
selectively, based at least in part on the signal (via 321, 322, 323), coupling a second supply voltage (ground) to the inverter; and
providing, by an output of the inverter, an updated version of the signal with an adjusted transition edge (column 7 lines 3-10 and 45-57).
Li does not specifically teach a capacitor coupled to the output of the single inverter.
Juang teaches a capacitor (24; Figure 2) coupled to the output of the single inverter (Sw1, Sw2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the capacitor taught by Juang in the circuit of Li to further calibrate the slew rate of the driving voltage (column 4 lines 65-67 and column 5 lines 1-2).
Juang further teaches that the capacitor is adjustable (column 4 lines 65-66). Li and Juang do not specifically teach a switch circuit coupled between the output of the single inverter and the capacitor.
Culler teaches a switch circuit (225, 235, 245; Figure 2) coupled between the output of the single inverter (215 corresponding to outp of Li) and the capacitor (220, 230, 240 corresponding to the adjustable capacitance 24 of Juang).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the switch circuit taught by Culler in the circuit of Li and Juang to further control the slew rate using capacitive elements (column 3 lines 10-15).
Claim 19: Li further teaches turning on a first number of p-type metal-oxide-semiconductor (PMOS) transistors (311, 312) to selectively couple the first supply voltage to the inverter, the first number determined based on the signal (via inp, Vpres and Vpcorner); and
turning on a second number of n-type metal-oxide-semiconductor (NMOS) transistors (321, 322) to selectively couple the second supply voltage (ground) to the inverter, the second number determined based on the signal (via inn, Vnres and Vncorner), wherein the first number and the second number are the same (two).
Claim 20: Li further teaches alternately turning on the PMOS transistors and the NMOS transistors (via inp and inn).
Claim(s) 5, 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Juang, in view of Culler and further in view of Lenhard et al. (U.S. Patent 8,067,974, hereafter Lenhard).
Claims 5 and 14: Li, Juang and Culler teach the limitations of claims 1 and 11 above.
Li, Juang and Culler do not specifically teach 2M switches. However, the selection of specific number of switches for the adjustable capacitance would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select 2M switches when employing the circuit of Li, Juang and Culler to maximize the overall performance of the circuit. Furthermore, such a provision of selecting a specific number of switches involves only routine design expedient.
Li, Juang and Culler do not specifically teach that the switch circuit (225, 235, 245; Figure 2 of Culler) includes transmission gates.
Lenhard teaches a switch circuit including transmission gates (Figure 3B; column 10 lines 55-59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the transmission gate taught by Lenhard in the circuit of Li, Juang and Culler to providing a low on-resistance value of the switch (column 10 lines 66-67).
Claim 6: The combined circuit further teaches that the each of the one or more de-skew stages is configured to adjust the transition edge of the signal with an adjustment resolution corresponding to a number of the transmission gates (Figure 3 of Juang).
Response to Arguments
Applicant's arguments filed January 6, 2026 have been fully considered but they are not persuasive.
Applicant asserts that Culler does not teach that the switch circuit is coupled between the output of the single inverter and the capacitor. Examiner respectfully disagrees. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this case, Li does not specifically teach a capacitor coupled to the output of the single inverter (313, 323; Figure 3 part of de-skew stages 301-303 that adjust a transition edge of a signal; column 7 lines 3-10 and 45-57 of Li). Juang teaches a capacitor (24; Figure 2) coupled to the output of the single inverter (Sw1, Sw2 form an inverter, corresponding to outp or outn of Li) to further calibrate the slew rate of the driving voltage (column 4 lines 65-67 and column 5 lines 1-2 of Juang). Juang further teaches that the capacitor is adjustable (column 4 lines 65-66). Culler teaches a switch circuit (225, 235, 245; Figure 2) coupled between the output of the single inverter (215 corresponding to outp of Li, where 215 is the signal line is where the slew adjustments are made; Abstract). Examiner notes that Applicant points to Figure 4 of Culler, which generates the control signals to the switches 225, 235 and 245 via a feedback mechanism. The inverters 410 and 430 of Culler are not referred to in the Office Action. Rather, signal line 215 of Culler corresponds to outp of Li, which is at the output of the single inverter in the combined circuit. Therefore, the combined circuit teaches a switch circuit coupled between the output of the single inverter and the capacitor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm.
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/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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