DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in respond to the amendment filed on 11/05/25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 1, the recitation “an input circuit including one or more cross-coupled transistors that provide a first control signal and a second control signal” on lines 2-3 is indefinite because it is not understood how “one transistor” can provide “a first control signal and a second control signal”, and the disclosure discloses that cross-couple transistor pairs (336 and 340 in Figure 2) provide the first control signal and the second control signal (A and B control signals, see specification, paragraph [0030]), so it is not clear if applicant means “cross-coupled transistor pairs”. Similarly, the recitation “second one or more cross-coupled transistors that receive a reference voltage signal, the first control signal, and the second control signal, the one or more cross-coupled transistors configured to output a first tracking signal and a second tracking signal to the cross-latch circuit” on the last 4 lines of the is indefinite for the similar reasons as discussed above since it is not clear how “second one transistor” can receive “a reference voltage signal, the first control signal, and the second control signal” since the disclosure clearly disclosure second cross-couple transistor pairs (332 and 334 in Figure 2) receiving “a reference voltage signal, the first control signal, and the second control signal” (see specification, paragraph [0032]). Furthermore, the recitation “the one or more cross-coupled transistors configured to output a first tracking signal and a second tracking signal to the cross-latch circuit” on the last 2 lines of the claim is indefinite because the claim already recited that the one or more cross-coupled transistors that provide a first control signal and a second control signal (see lines 2-3), so it is not understood why it is now also recited “the one or more cross-coupled transistors configured to output a first tracking signal and a second tracking signal to the cross-latch circuit”. Clarification and/or appropriate correction is required.
Claims 2-7 are indefinite because they depend on claim 1.
Also, for claim 2, the recitation “the reference voltage level” on lines 2 and 3 lack clear antecedent basis, and it is not clear if applicant means “the reference voltage signal” (see claim 1, line 10). Clarification and/or appropriate correction is required.
Claims 3-5 are also indefinite because they depend on claim 2.
Also, for claim 6, the recitation “wherein the tracking circuit includes: a first cross-coupled PMOS transistor pair; and a second cross-coupled PMOS transistor pair” is indefinite because it is not clear if “a first cross-coupled PMOS transistor pair; and a second cross-coupled PMOS transistor pair” of the tracking circuit recited in this claim are in addition to “second one or more cross-coupled transistors” recited earlier in claim 1 (note that claim 1 already recited” wherein the tracking circuit includes second one or more cross-coupled transistors”, see claim 1, lines 9-10). Clarification and/or appropriate correction is required.
For claim 8, the newly added limitations cause claim to be indefinite for the following reasons:
Because the claim recites “a first cross-coupled transistor pair connected to a gate of the second transistor” (line 3) so the second transistor is either transistor 318 or transistor 320 in Figure 2. Further, because the claim recites “a cross-latch circuit having a fifth transistor and a sixth transistor” (line 6), so from Figure 2, the cross-latch 110 having a fifth transistor (210) and a sixth transistor (214); and thus the recitations “a terminal of the fifth transistor coupled to a terminal of the second transistor” (line 6-7) and “wherein a coupling of the terminal of the fifth transistor and the terminal of the second transistor forms a first output terminal” (lines 8-9) are indefinite because a terminal of the fifth transistor (210) is not coupled to a terminal of the second transistor (either transistor 318 or transistor 320 because of the newly added limitation “a first cross-coupled transistor pair connected to a gate of the second transistor” recited on line 3 as discussed above), and Figure 2 does not show “wherein a coupling of the terminal of the fifth transistor (210) and the terminal of the second transistor (either 318 or 320) forms a first output terminal (Z)” as recited in the claim; and Figure 2 shows a terminal of the fifth transistor (210) is connected to a terminal of transistor 218 forms a first output terminal (Z), however, transistor 218 cannot be “a second transistor” in the claim (because of the newly added limitation “a first cross-coupled transistor pair connected to a gate of the second transistor” recited on line 3).
Furthermore, because the claim recites “a second cross-coupled transistor pair connected to a gate of the third transistor” (line 5) so the third transistor is either transistor 322 or transistor 324 in Figure 2; and because the claim recites “a terminal of the sixth transistor coupled to a terminal of the fourth transistor” (line 7-8) and “a coupling of the terminal of the sixth transistor and the terminal of the fourth transistor forms a second output terminal” so the fourth transistor is transistor 222 in Figure 2 (and because the sixth transistor is transistor 214 as discussed above); and thus the recitation “the tracking circuit further coupled to a node of the first transistor and the second transistor and a node of the third transistor and the fourth transistor” (lines11-13) is indefinite because Figure 2 shows the tracking circuit (332, 334) coupled to node A and node B, and node A is a node of transistor 318 and transistor 320, however, neither transistor 318 or transistor 320 is the second transistor of the claim (if the recitation “wherein a coupling of the terminal of the fifth transistor and the terminal of the second transistor forms a first output terminal” recites lines 8-9 is true); and node B is a node of transistor 322 and transistor 324, however the fourth transistor (as discussed above) is transistor 222 and transistor 222 is not connected to the tracking circuit (332, 334).
Furthermore, the recitation “the first node” on 13 lacks clear antecedent basis and it is not clear if applicant refers to “a node of the first transistor and the second transistor” recited earlier on line 12; and the recitation “the second node” on 14 lacks clear antecedent basis and it is not clear if applicant refers to “a node of the third transistor and the fourth transistor” recited earlier on line 13.
Clarification and/or appropriate correction is required.
Claims 9-14 are indefinite because they depend on claim 8.
Also, for claim 10, the recitations “the first input terminal” (line 1) and “the second input terminal” (line 2) both lack clear antecedent basis; and it is not clear if applicant means “a first input terminal of the first input circuit” and “a second input terminal of the second input circuit”, respectively; or whether applicant means “the first input circuit” and “the second input circuit”, respectively. Clarification and/or appropriate correction is required.
Also, for claim 14, the recitation “wherein the first transistor and the second transistor are NMOS” is indefinite because Figure 2 shows two NMOS transistors are 220 and 320, and if transistor 320 is the second transistor (because of the recitation “a first cross-coupled transistor pair connected to a gate of the second transistor” on line 3 of claim 8) then the first transistor is transistor 220. However, as analysis regarding the first and second transistors in claim 8 above, the first transistor 220 and the second transistor 320 will contradict with the limitations recited earlier in claim 8 (“wherein a coupling of the terminal of the fifth transistor and the terminal of the second transistor forms a first output terminal” (line 8-9, claim 8); and “the tracking circuit further coupled to a node of the first transistor and the second transistor and a node of the third transistor and the fourth transistor, wherein the first node is coupled to the first cross-coupled transistor pair and the second node is coupled to the second cross-coupled pair” (line 11-14, claim 8). Clarification and/or appropriate correction is required.
For claim 15, the recitation “wherein the control signals are generated by one or more cross-coupled transistors coupled to a transistor of the input circuit” on lines 3-4 is indefinite for the similar reasons as discussed in claim 1 above, i.e., it is not clear how “one cross-coupled transistor coupled to a transistor of the input circuit” can provide “a first control signal and a second control signal”, and the disclosure discloses that cross-couple transistor pairs (336 and 340 in Figure 2) provide the first control signal and the second control signal (A and B control signals, see specification, paragraph [0030]), so it is not clear if applicant means “cross-coupled transistor pairs, wherein each cross-coupled transistor pair coupled to a respective transistor”. Further, the recitation “comparing the control signals to a reference voltage signal by using second one or more cross-coupled transistors of the tracking circuit” (lines 6-7) is also indefinite for the similar reasons as discussed in claim 1 above, i.e., it is not clear how “second one transistor” can compares the control signals to a reference voltage signal since the disclosure clearly disclosure second cross-couple transistor pairs (332 and 334 in Figure 2) receiving for comparing the control signals to the reference voltages to generate the tracking signals (see specification, paragraph [0032]).
Claims 16-20 are indefinite because they depend on claim 15.
Response to Arguments
Applicant’s arguments filed on 11/05/25 have been considered but are moot in view of the new ground of rejection.
Conclusion
Because the scope of claims 1-20 cannot be determined due to the indefinite problems as discussed above under 35 U.S.C. 112(b) rejection(s), no prior art rejection can be applied against the claims at this time. Note that this is not an indication of allowability.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan, can be reached at (571) 272-1988. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842