Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Maejima (US Pub # 2016/0260487).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Maejima teaches a semiconductor device comprising: one or more first source switches configured to control a connection between a global source line and a first local source line (see Fig. 13, paragraph 0152-0159 where first switch 262a is coupled between local source line SL(0) and global line VERA); one or more second source switches configured to control a connection between the global source line and a second local source line (see Fig. 13, paragraph 0152-0159 where first switch 262b is coupled between local source line SL(1) and global line VERA); a first memory block configured to operate using a first source voltage supplied through the first local source line; a second memory block configured to operate using a second source voltage supplied through the second local source line (see Fig. 13, 15, paragraph 0152-0159 where voltage VERA is applied to VERA line); a first source pass transistor configured to control the first source switch in response to a first block select signal; and a second source pass transistor configured to control the second source switch in response to a second block select signal (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0202 where transistors ST2 are pass transistors, controlling switch 262a, 262b through source line SL).
Even though Maejima teaches source side transistor to control source switch but silent exclusively about pass transistor. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Maejima where source side transistor ST2 are coupled and controlling source switches and function as a pass transistor in order to reduce power consumption for the device (see paragraph 0036).
Regarding claim 2, Maejima teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Maejima further teaches, further comprising a voltage generation circuit configured to generate the first source voltage and the second source voltage and to supply the first source voltage and the second source voltage to the global source line (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0201).
Regarding claim 3, Maejima teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Maejima further teaches wherein the one or more first source switches include a plurality of first source switches coupled to the first local source line at different locations, and the first source voltage is supplied to the different locations of the first local source line through the plurality of first source switches (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185).
Regarding claim 4, Maejima teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Maejima further teaches, wherein the first source switch includes one or more transistors connected to each other in series between the global source line and the first local source line (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0190).
Regarding claim 5, Maejima teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Maejima further teaches, wherein during a read operation, the first local source line is pre-charged or discharged through the one or more first source switches (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0195).
Regarding claim 6, Maejima teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Maejima further teaches, further comprising: a global drain select line; and a drain select pass transistor configured to control a connection between the global drain select line and a drain select line of the first memory block (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0200).
Regarding claim 7, Maejima teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Maejima further teaches, further comprising: global word lines; word line pass transistors configured to control connections between the global word lines and word lines of the first memory block (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0187).
Regarding claim 8, Maejima teaches all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Maejima further teaches, further comprising: a global source select line; and a source select pass transistor configured to control a connection between the global source select line and a source select line of the first memory block (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0189).
Regarding independent claim 9, Maejima teaches a semiconductor device comprising: one or more first source switches configured to control a connection between a global source line and a first local source line (see Fig. 13, paragraph 0152-0159 where first switch 262a is coupled between local source line SL(0) and global line VERA); one or more second source switches configured to control a connection between the global source line and a second local source line (see Fig. 13, paragraph 0152-0159 where first switch 262b is coupled between local source line SL(1) and global line VERA); a memory block including a first sub-memory block configured to operate using a first source voltage supplied through the first local source line and a second sub-memory block configured to operate using a second source voltage supplied through the second local source line (see Fig. 13, 15, paragraph 0152-0159 where voltage VERA is applied to VERA line); a first source pass transistor configured to control the first source switch in response to a block select signal; and a second source pass transistor configured to control the second source switch in response to the block select signal (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0202 where transistors ST2 are pass transistors, controlling switch 262a, 262b through source line SL).
Even though Maejima teaches source side transistor to control source switch but silent exclusively about pass transistor. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Maejima where source side transistor ST2 are coupled and controlling source switches and function as a pass transistor in order to reduce power consumption for the device (see paragraph 0036).
Regarding claim 10, Maejima teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Maejima further teaches, further comprising a voltage generation circuit configured to generate the first source voltage and the second source voltage and to supply the first source voltage and the second source voltage to the global source line (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0191).
Regarding claim 11, Maejima teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Maejima further teaches, wherein the one or more first source switches include a plurality of first source switches coupled to the first local source line at different locations, and the first source voltage is supplied to the different locations of the first local source line through the plurality of first source switches (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0200).
Regarding claim 12, Maejima teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Maejima further teaches, wherein the one or more second source switches include a plurality of second source switches coupled to the second local source line at different locations, and the second source voltage is supplied to the different locations of the second local source line through the plurality of second source switches (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185).
Regarding claim 13, Maejima teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Maejima further teaches, wherein the first source switch includes one or more transistors connected to each other in series between the global source line and the first local source line (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0192).
Regarding claim 14, Maejima teaches all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Maejima further teaches, wherein during a read operation, the first local source line is pre-charged or discharged through the one or more first source switches (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0197).
Regarding independent claim 15, Maejima teaches a semiconductor device comprising: a gate structure including gate lines and insulating layers that are alternately stacked; a local source line located on the gate structure; source switches located on the local source line (see Fig. 13, paragraph 0152-0159 where first switch 262a is coupled between local source line SL(0) and global line VERA) and configured to control a connection between a global source line and the local source line; and a source pass transistor configured to control the source switches (see Fig. 13, paragraph 0152-0159 where first switch 262b is coupled between local source line SL(1) and global line VERA).
Even though Maejima teaches source side transistor to control source switch but silent exclusively about pass transistor. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Maejima where source side transistor ST2 are coupled and controlling source switches and function as a pass transistor in order to reduce power consumption for the device (see paragraph 0036).
Even though Maejima teaches selected and unselected block BLK but silent exclusively about block select signal. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Maejima where specific block is selected for operation i.e. block activation signal must be there to select the block in order to reduce power consumption for the device (see paragraph 0036).
Regarding claim 16, Maejima teaches all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Maejima further teaches, further comprising: a peripheral circuit; and a first bonding structure located between the peripheral circuit and the gate structure (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0199).
Regarding claim 17, Maejima teaches all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Maejima further teaches, further comprising a second bonding structure electrically connecting the source switches and the local source line to each other (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0194).
Regarding claim 18, Maejima teaches all claimed subject matter as applied in prior rejection of claim 15 on which this claim depends.
Maejima further teaches, wherein each of the source switches includes transistors stacked on the local source line (see Fig. 13, 15-19, paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0193).
Response to Arguments
Applicant's arguments filed 03/23/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 10 of remarks) that Maejima does not disclose, " The select transistor ST2 cannot control the first source switch 262a in response to a first block select signal.". Examiner respectfully disagrees with this statement.
Claim 1 recite “a first source pass transistor configured to control the first source switch in response to a first block select signal; and a second source pass transistor configured to control the second source switch in response to a second block select signal.”
First, as per claim, the source pass transistor would be the one that can control source switch.
Second, as per above claim limitation, the limitation “control” would be interpreted broadly as it didn’t specify what type of control (direct, indirect control, electrical, physical control etc.) i.e. if the source transistor can change source switch output, then it is controlling the switch.
In Fig. 2, 13, 15-19 and paragraph 0152-0159, 0167-0169, 0172-0182, 0185-0202, Maejima teach that ST2 transistor from first block SU0 is coupled between memory strings and source line SL. Also, first source switch 262a is coupled between first local source line SL0 of first block and global source line VERA and second source switch 262b is coupled between second local source line SL1 of second block and global source line VERA. When first source transistor ST2 is turned off by first control signal SGS0, it will disconnect all memory string of first Block from local and global source line where first source switch 262a no longer control the connection of memory string anymore. Similarly, second source switch 262b would be controlled by the source transistor of second block SU1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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