DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s continuity application filed on 11/17/2025.
Currently claims 11-30 are pending in the application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/15/2024, 05/02/2025 and 11/17/2025 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 13, 18-24 and 26 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
A. Claims 18–24
Claim 18 recites "wherein an elevation of a plane in which the upper electrode pad faces to the protective metal layer is placed between a lower surface of the first conductivity type semiconductor layer and a lower surface of the reflection layer." The phrase "faces to" renders the claim indefinite. First, the phrase is grammatically unclear. Second, and substantively, two elements that merely "face" each other are separated by a gap or an intervening layer and thereby define two distinct opposed surfaces — i.e., two candidate planes at different elevations. It cannot be determined which plane’s elevation must fall within the recited range, or whether physical contact (an interface, as with "adjoins" in claims 11 and 25) is required. The metes and bounds of the claim are therefore not reasonably ascertainable.
For purposes of applying prior art, "faces to" is interpreted consistent with the supporting disclosure ([0100] – [0106]) as "adjoins," i.e., the plane of the interface where the upper electrode pad contacts the protective metal layer. Claims 19–24 are rejected for depending from claim 18. Suggested amendment: replace "faces to" with "adjoins" for consistency with claims 11 and 25.
B. Claims 13, 20, and 26
Claims 13 and 20 recite "the support substrate has an electrical conductivity" (claim 26 contains the same recitation in combined form). Every material — including dielectrics — possesses a finite, non-zero electrical conductivity. As written, the limitation fails to distinguish a conductive substrate from an insulating one and thus fails to further limit the claim in a definite manner; one of ordinary skill cannot ascertain what degree of conductivity is required. For examination, the limitation is interpreted in light of the specification ([0007], [0070]) as "the support substrate is electrically conductive" (e.g., a metal or doped-semiconductor substrate capable of serving as a current path/lower electrode). Suggested amendment: "wherein the support substrate is electrically conductive."
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Examiner’s Note on Prior Arts - US 2019/0044027 A1 (Lee), published February 7, 2019; U.S. application 15/872,900 filed January 16, 2018 (KR priority to 10-2017-0007138, January 16, 2017); assigned to Seoul Viosys Co., Ltd.; corresponds to U.S. Patent 10,290,769. Lee qualifies as prior art under 35 U.S.C. 102(a)(1) (published before the 05/30/2019 effective filing date) and under 102(a)(2) (effectively filed at least by 01/16/2018, by another — the inventive entity of Lee (Mi Hee Lee, Joon Hee Lee, Chang Yeon Kim, Ju Yong Park, Jong Kyun You) differs from that of the instant application (Joon Hee Lee)).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0044027 A1 (Lee) and further in view of US 2016/0247971 A1 (Lee2).
Regarding claim 11, Lee discloses, a light emitting diode (100; light emitting diode; Figs. 1–2; [0082] – [0087]) comprising:
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a support substrate (support substrate 51; [0083]–[0084]; Fig. 2);
a first conductivity type semiconductor layer disposed on the support substrate (first conductivity type semiconductor layer 25, e.g., an n-type nitride semiconductor layer of semiconductor stack structure 30 disposed on support substrate 51; [0084]–[0085]);
an upper insulation layer disposed on the first conductivity type semiconductor layer (upper insulating layer 53 covering the upper and side surfaces of the first conductivity type semiconductor layer 25; [0103], [0132]);
a mesa comprising an active layer and a second conductivity type semiconductor layer and including a plurality of through-holes exposing the first conductivity type semiconductor layer (mesa M comprising active layer 27 and second conductivity type semiconductor layer 29 disposed under layer 25, the mesa having groove 32 formed through layers 29 and 27 to expose the first conductivity type semiconductor layer 25; [0086]–[0088]);
a first electrode disposed between the second conductivity type semiconductor layer and the support substrate and electrically connected to the first conductivity type semiconductor layer (first electrode 39 disposed between second insulating layer 37 and support substrate 51 — hence between layer 29 and substrate 51 — and electrically contacting layer 25 through the openings of insulating layers 31 and 37; [0096]–[0097]);
a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer (second electrode 34 comprising ohmic reflective layer 33 in ohmic contact with layer 29 and protective metal layer 35; the first electrode 39 is disposed between the second electrode 34 and the support substrate 51; [0091]–[0093], [0096]);
an upper electrode pad spaced apart from the second conductivity type semiconductor layer and electrically connected to the second electrode (upper electrode pad 55 separated from the semiconductor stack structure 30 in the horizontal direction and connected to the protective metal layer 35 of second electrode 34; [0104]–[0106]);
a first insulation layer disposed between the mesa and the support substrate and (first insulating layer 31 disposed between semiconductor stack structure 30/mesa M and support substrate 51; [0089]–[0090]);
a second insulation layer interposed between the first electrode and the second electrode (second insulating layer 37 covering protective metal layer 35 and interposed between first electrode 39 and second electrode 34; [0094]–[0096]),
wherein the plurality of through-holes are surrounded by the active layer and the second conductivity type semiconductor layer and are disposed within a region surrounded by edges of the mesa (the groove 32 penetrates layers 27/29 in the interior of mesa M, spaced from the mesa and substrate edges, [0087]; the fully "surrounded" plurality is supplied by Lee2 as combined below);
wherein the second electrode includes a protective metal layer extending outside the mesa and a reflection layer disposed between the protective metal layer and the second conductivity type semiconductor layer (the protective metal layer 35 ... covers the first insulating layer 31 and extends outside a region under the semiconductor stack structure 30, [0092]; the protective metal layer 35 covers the first insulating layer 31 around the mesa M and extends outside the mesa M. The protective metal layer 35 extending outside the mesa M is connected to the upper electrode pad 55, [0119]; ohmic reflective layer 33 — an Ag-based reflection layer — disposed between protective metal layer 35 and second conductivity type semiconductor layer 29, [0091]–[0092]);
wherein an elevation of a plane in which the upper electrode pad adjoins the protective metal layer is placed between a lower surface of the first conductivity type semiconductor layer and a lower surface of the reflection layer (an elevation of a plane in which the upper electrode pad 55 adjoins the protective metal layer 35 may be placed between the first conductivity type semiconductor layer 25 and the ohmic reflective layer 33, that is, in a region between the lower surface of the first conductivity type semiconductor layer 25 and a lower surface of the second conductivity type semiconductor layer 29, [0107]; because ohmic reflective layer 33 adjoins the lower surface of layer 29, a plane above the lower surface of layer 29 is necessarily above the lower surface of the reflection layer 33, and the disclosed elevation therefore lies within the claimed range);
But Lee fails to teach explicitly, a plurality of through-holes exposing the first conductivity type semiconductor layer, wherein the plurality of through-holes are surrounded by the active layer and the second conductivity type semiconductor layer and are disposed within a region surrounded by edges of the mesa (Lee’s illustrated interior n-contact is a single, partially open groove 32 rather than a plurality of enclosed through-holes; [0087]).
However, in analogous art, Lee2 discloses, a vertical light emitting diode in which mesas comprising the second conductive type semiconductor layer 115 and the active layer 113 are formed on the lower side of the light emitting structure 110 ([0044]); a plurality of second holes H2 (through-holes) formed in the mesa through layers 115 and 113 to expose the first conductive type semiconductor layer 111, wherein "multiple second holes H2 are illustrated as being regularly arranged at certain intervals in FIG. 1" within the interior of the mesa such that each hole is surrounded by the active layer and the second conductive type semiconductor layer within a region surrounded by the mesa edges (Figs. 1 and 2; [0045]); a first insulation layer 140 formed to surround the second holes H2 ([0052]); a first electrode 150a extending from electrode layer 150 and forming ohmic contact with the first conductive type semiconductor layer 111 through the second holes H2, such that current supplied through the electrode layer is injected into layer 111 at the plurality of hole locations ([0053]); the structure being supported on a conductive support substrate 170 (e.g., a Mo/Cu metal substrate) ([0057]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee and Lee2 before him/her, to modify the teachings of a light emitting diode as taught by Lee and to include the teachings of a plurality of through-holes formed through the second conductivity type semiconductor layer and the active layer within the interior of the mesa, each surrounded by the active layer and the second conductivity type semiconductor layer, with the first electrode contacting the first conductivity type semiconductor layer through the plurality of through-holes, as taught by Lee2, since distributing the n-side contact at a plurality of regularly spaced, enclosed locations across the mesa interior spreads electric current evenly over a large light emitting area and constitutes a simple substitution of one known interior n-contact geometry (a partially open groove) for another (a plurality of via-holes) yielding the predictable result of distributed current injection. Absent this important teaching in Lee, a person with ordinary skill in the art would be motivated to reach out to Lee2 while forming a light emitting diode of Lee.
Regarding claim 12, the combination of Lee and Lee2 discloses, the light emitting diode of claim 11, wherein a lateral area of the support substrate is greater than a lateral area of the first conductivity type semiconductor layer (the support substrate 51 has a larger area than the semiconductor stack structure 30. The semiconductor stack structure 30 is disposed in a region surrounded by an edge of the support substrate 51; [0084]; Figs. 1–2).
Regarding claim 13, Lee further discloses, wherein the support substrate has an electrical conductivity (if the support substrate 51 is a conductive substrate, the support substrate 51 can act as a lower electrode pad; [0102]; see also Lee2, [0057], conductive Mo/Cu support substrate 170).
Regarding claim 14, Lee further discloses, wherein the reflection layer is confined in a region under the mesa (the ohmic reflective layer 33 is confined in a region under the mesa M; [0091]).
Regarding claim 15, Lee further discloses, wherein the upper electrode pad is disposed near a corner of the support substrate and is separated from the first conductivity type semiconductor layer (the upper electrode pad 55 may be disposed near one corner of the support substrate 51, [0105]; the pad 55 is separated from the semiconductor stack structure 30 in the horizontal direction and is insulated from the first conductivity type semiconductor layer 25, [0104], [0106]).
Regarding claim 16, Lee further discloses, wherein the first conductivity type semiconductor layer includes a roughened upper surface covered by the upper insulation layer (roughened surface R formed on the upper surface of layer 25, [0085], [0130]; the upper insulating layer 53 covers the roughened surface R and may be formed along roughness of the roughened surface R, [0103], [0132]).
Regarding claim 17, the combination of Lee and Lee2 discloses, wherein the first electrode includes first contact portions electrically connected to the first conductivity type semiconductor layer through the plurality of through-holes (Lee: first electrode 39 including contact portions 39a/39b connected to layer 25, [0097]–[0098]; Lee2: first electrode 150a in ohmic contact with layer 111 through the plurality of second holes H2, [0053]; in the combination the interior contact portions of Lee’s first electrode 39 extend through the plurality of through-holes taught by Lee2). The motivation to combine is the same as set forth for claim 11.
Claims 18–24 rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0044027 A1 (Lee) and further in view of US 2016/0247971 A1 (Lee2)
Regarding claim 18, Lee discloses, a light emitting module (light emitting module 1020 of the lighting apparatus of FIG. 21; [0223]) comprising: a substrate including a conductive pattern (substrate 1023, wherein "the substrate 1023 may include a printed circuit board having interconnects formed thereon" — the interconnects constituting the conductive pattern; FIG. 21 and accompanying description);
a light emitting device disposed on the substrate and electrically connected to the conductive pattern, the light emitting device including a light emitter (light emitting device 1021 disposed on substrate 1023 and electrically connected through the substrate to power supply 1033, wherein device 1021 "may include at least one of the light emitting diodes according to the exemplary embodiments described above," i.e., the light emitting diode of Figs 1-2; Fig. 21; [0223] – [0226]);
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the light emitting diode (100; light emitting diode; Figs. 1–2; [0082] – [0087]) comprising: a support substrate (support substrate 51; [0083]–[0084]; Fig. 2);
a first conductivity type semiconductor layer disposed on the support substrate (first conductivity type semiconductor layer 25, e.g., an n-type nitride semiconductor layer of semiconductor stack structure 30 disposed on support substrate 51; [0084]–[0085]);
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an upper insulation layer disposed on the first conductivity type semiconductor layer (upper insulating layer 53 covering the upper and side surfaces of the first conductivity type semiconductor layer 25; [0103], [0132]);
a mesa comprising an active layer and a second conductivity type semiconductor layer and including a plurality of through-holes exposing the first conductivity type semiconductor layer (mesa M comprising active layer 27 and second conductivity type semiconductor layer 29 disposed under layer 25, the mesa having groove 32 formed through layers 29 and 27 to expose the first conductivity type semiconductor layer 25; [0086]–[0088]);
a first electrode disposed between the second conductivity type semiconductor layer and the support substrate and electrically connected to the first conductivity type semiconductor layer (first electrode 39 disposed between second insulating layer 37 and support substrate 51 — hence between layer 29 and substrate 51 — and electrically contacting layer 25 through the openings of insulating layers 31 and 37; [0096]–[0097]);
a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to electrically connected to the second conductivity type semiconductor layer (second electrode 34 comprising ohmic reflective layer 33 in ohmic contact with layer 29 and protective metal layer 35; the first electrode 39 is disposed between the second electrode 34 and the support substrate 51; [0091]–[0093], [0096]);
an upper electrode pad spaced apart from the second conductivity type semiconductor layer and electrically connected to the second conductivity type semiconductor layer (pad 55 is connected to protective metal layer 35, which is electrically connected to layer 29 through ohmic reflective layer 33 — hence electrically connected to the second conductivity type semiconductor layer; [0091]–[0093], [0104]);
a first insulation layer disposed between the mesa and the support substrate and (first insulating layer 31 disposed between semiconductor stack structure 30/mesa M and support substrate 51; [0089]–[0090]);
a second insulation layer interposed between the first electrode and the second electrode (second insulating layer 37 covering protective metal layer 35 and interposed between first electrode 39 and second electrode 34; [0094]–[0096]),
wherein the plurality of through-holes are surrounded by the active layer and the second conductivity type semiconductor layer and are disposed within a region surrounded by edges of the mesa (the groove 32 penetrates layers 27/29 in the interior of mesa M, spaced from the mesa and substrate edges, [0087]; the fully "surrounded" plurality is supplied by Lee2 as combined below);
wherein the second electrode includes a protective metal layer extending outside the mesa and a reflection layer covered by the protective metal layer; and ([0092]: "The protective metal layer 35 is disposed between the ohmic reflective layer 33 and the support substrate 51 and covers the ohmic reflective layer 33"; [0119]: protective metal layer 35 extends outside the mesa M);
wherein an elevation of a plane in which the upper electrode pad faces to the protective metal layer is placed between a lower surface of the first conductivity type semiconductor layer and a lower surface of the reflection layer (an elevation of a plane in which the upper electrode pad 55 adjoins the protective metal layer 35 may be placed between the first conductivity type semiconductor layer 25 and the ohmic reflective layer 33, that is, in a region between the lower surface of the first conductivity type semiconductor layer 25 and a lower surface of the second conductivity type semiconductor layer 29, [0107]; because ohmic reflective layer 33 adjoins the lower surface of layer 29, a plane above the lower surface of layer 29 is necessarily above the lower surface of the reflection layer 33, and the disclosed elevation therefore lies within the claimed range);
But Lee fails to teach explicitly, a plurality of through-holes exposing the first conductivity type semiconductor layer, wherein the plurality of through-holes are surrounded by the active layer and the second conductivity type semiconductor layer and are disposed within a region surrounded by edges of the mesa (Lee’s illustrated interior n-contact is a single, partially open groove 32 rather than a plurality of enclosed through-holes; [0087]).
However, in analogous art, Lee2 discloses, a vertical light emitting diode in which mesas comprising the second conductive type semiconductor layer 115 and the active layer 113 are formed on the lower side of the light emitting structure 110 ([0044]); a plurality of second holes H2 (through-holes) formed in the mesa through layers 115 and 113 to expose the first conductive type semiconductor layer 111, wherein "multiple second holes H2 are illustrated as being regularly arranged at certain intervals in FIG. 1" within the interior of the mesa such that each hole is surrounded by the active layer and the second conductive type semiconductor layer within a region surrounded by the mesa edges (Figs. 1 and 2; [0045]); a first insulation layer 140 formed to surround the second holes H2 ([0052]); a first electrode 150a extending from electrode layer 150 and forming ohmic contact with the first conductive type semiconductor layer 111 through the second holes H2, such that current supplied through the electrode layer is injected into layer 111 at the plurality of hole locations ([0053]); the structure being supported on a conductive support substrate 170 (e.g., a Mo/Cu metal substrate) ([0057]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee and Lee2 before him/her, to modify the teachings of a light emitting diode as taught by Lee and to include the teachings of a plurality of through-holes formed through the second conductivity type semiconductor layer and the active layer within the interior of the mesa, each surrounded by the active layer and the second conductivity type semiconductor layer, with the first electrode contacting the first conductivity type semiconductor layer through the plurality of through-holes, as taught by Lee2, since distributing the n-side contact at a plurality of regularly spaced, enclosed locations across the mesa interior spreads electric current evenly over a large light emitting area and constitutes a simple substitution of one known interior n-contact geometry (a partially open groove) for another (a plurality of via-holes) yielding the predictable result of distributed current injection. Absent this important teaching in Lee, a person with ordinary skill in the art would be motivated to reach out to Lee2 while forming a light emitting diode of Lee.
Regarding claim 19, the combination of Lee and Lee2 discloses, the light emitting module of claim 18, wherein a lateral area of the support substrate is greater than a lateral area of the first conductivity type semiconductor layer (the support substrate 51 has a larger area than the semiconductor stack structure 30. The semiconductor stack structure 30 is disposed in a region surrounded by an edge of the support substrate 51; [0084]; Figs. 1–2).
Regarding claim 20, Lee further discloses, wherein the support substrate has an electrical conductivity (if the support substrate 51 is a conductive substrate, the support substrate 51 can act as a lower electrode pad; [0102]; see also Lee2, [0057], conductive Mo/Cu support substrate 170).
Regarding claim 21, Lee further discloses, wherein the reflection layer is confined in a region under the mesa (the ohmic reflective layer 33 is confined in a region under the mesa M; [0091]).
Regarding claim 22, Lee further discloses, wherein the upper electrode pad is disposed near a corner of the support substrate and is separated from the first conductivity type semiconductor layer (the upper electrode pad 55 may be disposed near one corner of the support substrate 51, [0105]; the pad 55 is separated from the semiconductor stack structure 30 in the horizontal direction and is insulated from the first conductivity type semiconductor layer 25, [0104], [0106]).
Regarding claim 23, Lee further discloses, wherein the first conductivity type semiconductor layer includes a roughened upper surface covered by the upper insulation layer (roughened surface R formed on the upper surface of layer 25, [0085], [0130]; the upper insulating layer 53 covers the roughened surface R and may be formed along roughness of the roughened surface R, [0103], [0132]).
Regarding claim 24, the combination of Lee and Lee2 discloses, wherein the first electrode includes first contact portions electrically connected to the first conductivity type semiconductor layer through the plurality of through-holes (Lee: first electrode 39 including contact portions 39a/39b connected to layer 25, [0097]–[0098]; Lee2: first electrode 150a in ohmic contact with layer 111 through the plurality of second holes H2, [0053]; in the combination the interior contact portions of Lee’s first electrode 39 extend through the plurality of through-holes taught by Lee2).
Claims 25–30 rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0044027 A1 (Lee) and further in view of US 2016/0247971 A1 (Lee2).
Regarding claim 25, Lee discloses, a light emitting apparatus (light emitting module 1020 of the lighting apparatus of FIG. 21; [0223]) comprising: a substrate including a conductive pattern (substrate 1023, wherein "the substrate 1023 may include a printed circuit board having interconnects formed thereon" — the interconnects constituting the conductive pattern; FIG. 21 and accompanying description);
a light emitting device disposed on the substrate and electrically connected to the conductive pattern, the light emitting device including a light emitter (light emitting device 1021 disposed on substrate 1023 and electrically connected through the substrate to power supply 1033, wherein device 1021 "may include at least one of the light emitting diodes according to the exemplary embodiments described above," i.e., the light emitting diode of Figs 1-2; Fig. 21; [0223] – [0226]);
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the light emitting diode (100; light emitting diode; Figs. 1–2; [0082] – [0087]) comprising:
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a support substrate (support substrate 51; [0083]–[0084]; Fig. 2);
a first conductivity type semiconductor layer disposed on the support substrate (first conductivity type semiconductor layer 25, e.g., an n-type nitride semiconductor layer of semiconductor stack structure 30 disposed on support substrate 51; [0084]–[0085]);
an upper insulation layer disposed on the first conductivity type semiconductor layer (upper insulating layer 53 covering the upper and side surfaces of the first conductivity type semiconductor layer 25; [0103], [0132]);
a mesa comprising an active layer and a second conductivity type semiconductor layer and including a plurality of through-holes exposing the first conductivity type semiconductor layer (mesa M comprising active layer 27 and second conductivity type semiconductor layer 29 disposed under layer 25, the mesa having groove 32 formed through layers 29 and 27 to expose the first conductivity type semiconductor layer 25; [0086]–[0088]);
a first electrode disposed between the second conductivity type semiconductor layer and the support substrate and electrically connected to the first conductivity type semiconductor layer (first electrode 39 disposed between second insulating layer 37 and support substrate 51 — hence between layer 29 and substrate 51 — and electrically contacting layer 25 through the openings of insulating layers 31 and 37; [0096]–[0097]);
a second electrode disposed between the first electrode and the second conductivity type semiconductor layer and electrically connected to electrically connected to the second conductivity type semiconductor layer (second electrode 34 comprising ohmic reflective layer 33 in ohmic contact with layer 29 and protective metal layer 35; the first electrode 39 is disposed between the second electrode 34 and the support substrate 51; [0091]–[0093], [0096]);
an upper electrode pad spaced apart from the second conductivity type semiconductor layer and electrically connected to the second electrode (upper electrode pad 55 separated from the semiconductor stack structure 30 in the horizontal direction and connected to the protective metal layer 35 of second electrode 34; [0104]–[0106]);
a first insulation layer disposed between the mesa and the support substrate and (first insulating layer 31 disposed between semiconductor stack structure 30/mesa M and support substrate 51; [0089]–[0090]);
a second insulation layer interposed between the first electrode and the second electrode (second insulating layer 37 covering protective metal layer 35 and interposed between first electrode 39 and second electrode 34; [0094]–[0096]),
wherein the plurality of through-holes are surrounded by the active layer and the second conductivity type semiconductor layer and are disposed within a region surrounded by edges of the mesa (the groove 32 penetrates layers 27/29 in the interior of mesa M, spaced from the mesa and substrate edges, [0087]; the fully "surrounded" plurality is supplied by Lee2 as combined below);
wherein the second electrode includes a protective metal layer extending outside the mesa and a reflection layer covered by the protective metal layer; and ([0092]: "The protective metal layer 35 is disposed between the ohmic reflective layer 33 and the support substrate 51 and covers the ohmic reflective layer 33"; [0119]: protective metal layer 35 extends outside the mesa M);
wherein an elevation of a plane in which the upper electrode pad adjoins the protective metal layer is lower than a lower surface of the first conductivity type semiconductor layer ("a bottom surface of the upper electrode pad 55 is placed under the lower surface of the first conductivity type semiconductor layer 25"; [0107]).
But Lee fails to teach explicitly, a plurality of through-holes exposing the first conductivity type semiconductor layer, wherein the plurality of through-holes are surrounded by the active layer and the second conductivity type semiconductor layer and are disposed within a region surrounded by edges of the mesa (Lee’s illustrated interior n-contact is a single, partially open groove 32 rather than a plurality of enclosed through-holes; [0087]).
However, in analogous art, Lee2 discloses, a vertical light emitting diode in which mesas comprising the second conductive type semiconductor layer 115 and the active layer 113 are formed on the lower side of the light emitting structure 110 ([0044]); a plurality of second holes H2 (through-holes) formed in the mesa through layers 115 and 113 to expose the first conductive type semiconductor layer 111, wherein "multiple second holes H2 are illustrated as being regularly arranged at certain intervals in FIG. 1" within the interior of the mesa such that each hole is surrounded by the active layer and the second conductive type semiconductor layer within a region surrounded by the mesa edges (Figs. 1 and 2; [0045]); a first insulation layer 140 formed to surround the second holes H2 ([0052]); a first electrode 150a extending from electrode layer 150 and forming ohmic contact with the first conductive type semiconductor layer 111 through the second holes H2, such that current supplied through the electrode layer is injected into layer 111 at the plurality of hole locations ([0053]); the structure being supported on a conductive support substrate 170 (e.g., a Mo/Cu metal substrate) ([0057]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee and Lee2 before him/her, to modify the teachings of a light emitting diode as taught by Lee and to include the teachings of a plurality of through-holes formed through the second conductivity type semiconductor layer and the active layer within the interior of the mesa, each surrounded by the active layer and the second conductivity type semiconductor layer, with the first electrode contacting the first conductivity type semiconductor layer through the plurality of through-holes, as taught by Lee2, since distributing the n-side contact at a plurality of regularly spaced, enclosed locations across the mesa interior spreads electric current evenly over a large light emitting area and constitutes a simple substitution of one known interior n-contact geometry (a partially open groove) for another (a plurality of via-holes) yielding the predictable result of distributed current injection. Absent this important teaching in Lee, a person with ordinary skill in the art would be motivated to reach out to Lee2 while forming a light emitting diode of Lee.
Regarding claim 26, the combination of Lee and Lee2 discloses, the light emitting diode of claim 25, wherein a lateral area of the support substrate is greater than a lateral area of the first conductivity type semiconductor layer (the support substrate 51 has a larger area than the semiconductor stack structure 30. The semiconductor stack structure 30 is disposed in a region surrounded by an edge of the support substrate 51; [0084]; Figs. 1–2).
Regarding claim 27, Lee further discloses, wherein the reflection layer is confined in a region under the mesa (the ohmic reflective layer 33 is confined in a region under the mesa M; [0091]).
Regarding claim 28, Lee further discloses, wherein the upper electrode pad is disposed near a corner of the support substrate and is separated from the first conductivity type semiconductor layer (the upper electrode pad 55 may be disposed near one corner of the support substrate 51, [0105]; the pad 55 is separated from the semiconductor stack structure 30 in the horizontal direction and is insulated from the first conductivity type semiconductor layer 25, [0104], [0106]).
Regarding claim 29, Lee further discloses, wherein the first conductivity type semiconductor layer includes a roughened upper surface covered by the upper insulation layer (roughened surface R formed on the upper surface of layer 25, [0085], [0130]; the upper insulating layer 53 covers the roughened surface R and may be formed along roughness of the roughened surface R, [0103], [0132]).
Regarding claim 30, the combination of Lee and Lee2 discloses, wherein the first electrode includes first contact portions electrically connected to the first conductivity type semiconductor layer through the plurality of through-holes (Lee: first electrode 39 including contact portions 39a/39b connected to layer 25, [0097]–[0098]; Lee2: first electrode 150a in ohmic contact with layer 111 through the plurality of second holes H2, [0053]; in the combination the interior contact portions of Lee’s first electrode 39 extend through the plurality of through-holes taught by Lee2).
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2019/0027649 A1 (Yoon) - A semiconductor light-emitting device includes a light-emitting structure, a reflective electrode layer, and a transparent cover layer. The light-emitting structure includes a first semiconductor layer, an active layer, and a second semiconductor layer. The reflective electrode layer covers an upper surface of the second semiconductor layer. The transparent cover layer covers an upper surface of the second semiconductor layer on the reflective electrode layer. The transparent cover layer includes a tail portion including a first portion and a second portion. The first portion covers an edge of the reflective electrode layer and a convex upper surface. The second portion is thinner than and extends from the first portion.
US 2017/0148946 A1 (Lee) - A light emitting device comprises a first light emitting part including at least one light emitting cell, a second light emitting part including a plurality of light emitting cells, wherein each of the light emitting cells include a light emitting structure and a first electrode layer disposed under the light emitting structure. It also comprises a plurality of pads disposed on the light emitting cell of the first light emitting part, wherein the pads are electrically connected to each of the light emitting cells of the first and second light emitting parts; a plurality of connection layers, each connection layer extending from a region under the light emitting cell of the first light emitting part to a region under the plurality of light emitting cells of the second light emitting part; a second electrode layer disposed under the light emitting cells of the first and second light emitting parts.
US 2014/0367722 A1 (Im) - A light-emitting diode is disclosed that includes a first conductive clad layer, a light-scattering pattern configured, in the first conductive clad layer, having a refractive index different from that of the first conductive clad layer. It also includes an active layer located under the first conductive clad layer, a second conductive clad layer located under the active layer, a first electrode configured to be electrically connected to the first conductive clad layer, and a second electrode configured to be electrically connected to the second conductive clad layer. The light-scattering pattern can improve light extraction efficiency.
Conclusion
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
07/10/2026
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