Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR10-2023-0120612 filed on 9/11/2023. The foreign application is not in English. The certified copy of the foreign priority application has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application KR10-2023-0120612 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US Pub. 2023063886), hereinafter referred to as Jo, and Kim et al. (US Pub. 20230092410), hereinafter referred to as Kim.
Regarding claim 1, Jo teaches A semiconductor package comprising: a first semiconductor chip (Jo, 220 Fig. 3A, Fig. para. 85); a dummy die on the first semiconductor chip (Jo, 230, Fig. 3A, para. 85); second semiconductor chips stacked on the dummy die (Jo, 300, Fig. 3A, para. 85); and a dummy plate on the second semiconductor chips (Jo, 400, Fig. 3A, para. 87, Jo refers to 400 as a heat dissipation structure, however, it may contain Si or Ge (para. 66) which are the same materials listed for dummy plate 400, which is also used for heat dissipation (see para. 84 of the application)), wherein each of the first semiconductor chip, the dummy die, and the second semiconductor chips comprises through-electrodes (Jo, para. 42, states that 200 (which contains first semiconductor die 220 and dummy die 230), contains through electrodes, para. 33 states that third semiconductor die 300 may also contain through electrodes), wherein the dummy die and a lowermost one among the second semiconductor chips, closest to the dummy die, are connected to each other by direct contact of first bonding pads (Jo, para. 85, states that the dummy die, 230 may be disposed between semiconductor die 220 and semiconductor dies 300, further para. 58 and 88 shows the that semiconductor 220 die, dummy die 230 and semiconductor die 300 may all connect using direct contact of the bonding pad), wherein adjacent ones of the second semiconductor chips are connected to each other by direct contact of second bonding pads (Jo, para. 61), wherein the first semiconductor chip, the dummy die, the second semiconductor chips and the dummy plate have a first width, a second width, a third width, and a fourth width in a horizontal direction, respectively (Jo, Fig. 3A, see diagram below), and wherein the fourth width is greater than the third width (Jo, Fig. 3A, see diagram below).
Jo does not teach wherein the fourth width is greater than the second width.
However, Kim teaches a semi-conductor device with a dummy die (Kim, 300, Fig. 4A, para. 51) of the same size as the second semiconductor die (Kim, 200A, Fig. 4A para. 51).
Therefore, it would have been obvious to a person of ordinary skill in the art to modify the dummy chip of Jo to the size of Kim in order to improve the dispersal of heat between the first and second semiconductor dies (Kim, para. 30).
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Regarding claim 2, modified Jo teaches the semiconductor package of claim 1, wherein the first width is substantially equal to the fourth width (Jo, Fig. 3A, para. 71, side surfaces of semiconductor die 220, molding layer 500, and heat dissipation structure 400 a are all coplanar, ergo equal width).
Regarding claim 3, modified Jo teaches the semiconductor package of claim 1, wherein the second width is substantially equal to the third width (Kim, 300, 200, Fig. 4A)
Regarding claim 4, modified Jo teaches the semiconductor package of claim 1, wherein the dummy die does not comprise an integrated circuit and an interconnection pattern (Kim, para. 30, describes the dummy chip as lacking active or passive devices).
Regarding claim 7, modified Jo teaches the semiconductor package of claim 1, wherein the first semiconductor chip has a first thickness (Jo, 220, Fig. 3A, paras. 50-52),
wherein the dummy die has a second thickness (Jo, 230, Fig. 3A, para. 89),
wherein each of the second semiconductor chips has a third thickness (Jo, Jo, 300, Fig. 3A, paras. 50-52),
wherein the dummy plate has a fourth thickness (Jo, 400, Fig. 3A, para. 65).
Jo does not explicitly teach wherein the fourth thickness is three times or more greater than each of the first thickness, the second thickness, and the third thickness.
However, Jo acknowledges that when the heat dissipation structure is thick, the heat of the semiconductor package may be more easily dissipated (Jo, para. 65).
Thus, the thickness of the heat dissipation structure is not merely a process parameter, but a result affective variable.
If too low, heat will be retained and damage to the device may occur.
If too high, material costs will rise and the device may become too large.
Within the optimal window heat dissipation is optimized and costs and size would be balanced with performance.
Because the prior art recognizes that the thickness of the heat dissipation structure directly affects heat dissipation and the size of the structure affects device size, the thickness is a result affective variable. Therefore it would have been obvious for one of ordinary skill in the art before the filing date of the invention to optimize this variable through routine experimentation. The selection of a fourth thickness three times or greater the thickness of the first and second semiconductor dies and the dummy chip would be a predictable result of such optimization, absent evidence of unexpected results or criticality associated with the three times thickness threshold. (See MPEP 2144.05 II).
Claims 15, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jo and Lin et al ( US Pub. 20230352361), hereinafter referred to as Jin.
Regarding claim 15, Jo teaches a semiconductor package comprising: a first semiconductor chip (Jo, 220 Fig. 3A, Fig. para. 85); a dummy die on the first semiconductor chip (Jo, 230, Fig. 3A, para. 85); second semiconductor chips stacked on the dummy die (Jo, 300, Fig. 3A, para. 85); a dummy plate on the second semiconductor chips (Jo, 400, Fig. 3A, para. 87, Jo refers to 400 as a heat dissipation structure, however, it may contain Si or Ge (para. 66) which are the same materials listed for dummy plate 400, which is also used for heat dissipation (see para. 84 of the application)); and a molding structure between the first semiconductor chip and the dummy plate (Jo, 500, Fig. 3A, para. 70), wherein each of the first semiconductor chip, the dummy die, and the second semiconductor chips comprises through-electrodes (Jo, para. 42, states that 200 (which contains first semiconductor die 220 and dummy die 230), contains through electrodes, para. 33 states that third semiconductor die 300 may also contain through electrodes), wherein the dummy die and the first semiconductor chip are connected to each other by direct contact of first bonding pads (Jo, para. 85, states that the dummy die, 230 may be disposed between semiconductor die 220 and semiconductor dies 300, further para. 58 and 88 shows the that semiconductor 220 die, dummy die 230 and semiconductor die 300 may all connect using direct contact of the bonding pad), wherein the dummy die and a lowermost one among the second semiconductor chips are connected to each other by direct contact of second bonding pads (Jo, para. 85, states that the dummy die, 230 may be disposed between semiconductor die 220 and semiconductor dies 300, further para. 58 and 88 shows the that semiconductor 220 die, dummy die 230 and semiconductor die 300 may all connect using direct contact of the bonding pad), wherein adjacent ones of the second semiconductor chips are connected to each other by direct contact of third bonding pads (Jo, para. 61), and wherein the molding structure is on a top surface of the first semiconductor chip, a side surface of the dummy die, side surfaces of the second semiconductor chips, and a bottom surface of the dummy plate (Jo para. 86).
Jo does not explicitly teach wherein the heat dissipation structure and an uppermost one among the second semiconductor chips are connected to each other by direct contact of insulating materials.
Jo does teach wherein the dummy plate and an uppermost one among the second semiconductor chips are connected to each other by a thermal interface material (TIM) (Jo, para. 69).
Additionally Lin (Lin para. 17) states that a TIM may be silicon oxide, which is the same material claimed for the adhesive insulating material in para. 50 of the application and claim 16 below.
Therefore it would have been obvious to use a known material as the TIM in order to provide good thermal conductivity (Lin, para. 17 shows 3 W/mK and 15 W/mK or even higher) to allow the heat dissipation structure to operate efficiently.
Regarding claim 16, modified Jo teaches the semiconductor package of claim 15, wherein the dummy plate comprises silicon (Jo, para. 86), and wherein the insulating materials comprises silicon oxide (Jo, para. 69 shows the connection is via TIM, and Lin para. 17 shows that a TIM may be silicon oxide).
Regarding claim 18, modified Jo teaches does not explicitly teach the semiconductor package of claim 15, wherein a thickness of the dummy plate is 250 µm or more.
However, Jo does teach wherein the heat dissipation structure (Jo, 400, Fig. 3A) has a thickness greater than the first semiconductor die (Jo, para. 65). Joe further teaches thickness of the first semiconductor chip may be about 95 µm (Jo, para. 51). Finally, Jo acknowledges that when the heat dissipation structure is thick, the heat of the semiconductor package may be more easily dissipated (Jo, para. 65).
Thus, the thickness of the heat dissipation structure is not merely a process parameter, but a result affective variable.
If too low, heat will be retained and damage to the device may occur.
If too high, material costs will rise and the device may become too large.
Within the optimal window heat dissipation is optimized and costs and size would be balanced with performance.
Because the prior art recognizes that the thickness of the heat dissipation structure directly affects heat dissipation and the size of the structure affects device size, the thickness is a result affective variable. Therefore it would have been obvious for one of ordinary skill in the art before the filing date of the invention to optimize this variable through routine experimentation. The selection of a fourth thickness three times or greater the thickness of the first and second semiconductor dies and the dummy chip would be a predictable result of such optimization, absent evidence of unexpected results or criticality associated with the three times thickness threshold. (See MPEP 2144.05 II).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jo, Kim and Lin.
Regarding claim 20, Jo teaches a semiconductor package comprising: a package substrate (Jo, 700, Fig. 4, para. 108); an interposer on the package substrate (Jo, 100, Figs. 3A, 4, paras. 85, 108); a logic chip on the interposer (Jo, 600, Fig. 4, para. 108); and chip stack structures spaced apart from each other with the logic chip interposed there between (Jo, Fig. 4, para. 109), wherein each of the chip stack structures comprises: a buffer die (Jo, 210, Fig. 3A, 4, para. 32); a dummy die on the buffer die (Jo, 230, Fig. 3A, paras. 85, 120); core dies stacked on the dummy die (Jo, 300, Fig. 3A, 4, para. 85; a dummy plate on the core dies (Jo, 400, Figs. 3A, 4, para. 87); and a molding structure between the buffer die and the dummy plate (Jo, 500, Figs. 3A, 4, para. 113), wherein each of the buffer die, the dummy die, and the core dies comprises through-electrodes (Jo, para. 42, states that 200 (which contains first semiconductor die 220 and dummy die 230), contains through electrodes, para. 33 states that third semiconductor die 300 may also contain through electrodes), wherein adjacent ones of the core dies are connected to each other by direct contact of third bonding pads (Jo, para. 61), wherein the molding structure is on a top surface of the buffer die, a side surface of the dummy die, side surfaces of the core dies, and a bottom surface of the dummy plate (Jo, para. 86), wherein the buffer die, the dummy die, the core dies, and the dummy plate have a first width, a second width, a third width, and a fourth width in a horizontal direction, respectively (Jo, Fig. 3A, see diagram below),
Joe does not explicitly teach; wherein the dummy die and the buffer die are connected to each other by direct contact of first bonding pads, wherein the dummy die and a lowermost one among the core dies are connected to each other by direct contact of second bonding pads wherein the dummy plate and an uppermost one among the core dies are connected to each other by direct contact of insulating materials and wherein the first width is substantially equal to the fourth width, and wherein the second width is substantially equal to the third width.
Jo does teach wherein the dummy plate and an uppermost one among the second semiconductor chips are connected to each other by a thermal interface material (TIM) (Jo, para. 69).
Additionally Lin (Lin para. 17) states that a TIM may be silicon oxide, which is the same material claimed for the adhesive insulating material in para. 50 of the application and claim 16 below.
Therefore it would have been obvious to use a known material as the TIM in order to provide good thermal conductivity (Lin, para. 17 shows 3 W/mK and 15 W/mK or even higher) to allow the heat dissipation structure to operate efficiently.
Jo additionally teaches that connections between semiconductor dies 210, 220, 300 and dummy die may be done by direct connection of contact pads (Jo, paras. 58, 88). Jo further teaches that dummy die 230 may be situated in above, below or in between dies 210 and 230 (Jo, para. 85) but does not state that there is a direct physical connection from buffer die 210 to dummy die 230 to semiconductor die 300. Jo also teaches wherein the first width is substantially equal to the fourth width (Jo, Fig. 3A, para. 71, side surfaces of semiconductor die 220, molding layer 500, and heat dissipation structure 400 a are all coplanar, ergo equal width).
However, Kim teaches a semiconductor device with a buffer chip (Kim, 100, Fig. 3A, para. 34) a dummy chip (Kim, 300, Fig. 3A, para. 49) and a memory stack (Kim, 200A-D, Fig. 3A, para. 36) wherein there is a direct connection from the buffer chip to the dummy chip to the memory stack, and wherein the dummy chip has the same width as the memory stack chips (Kim, 200, 300, Fig. 3A)
Therefore, it would have been obvious to a person of ordinary skill in the art to modify the dummy chip of Jo to the size of Kim and use the configuration of Kim wherein the buffer chip directly contacts the dummy die and the dummy die is next to the memory stack with no intervening semiconductor layer in order to in order to improve the dispersal of heat between the buffer die and core dies (Kim, para. 30).
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Allowable Subject Material
Claim s 5, 6, 8-14, 17 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following are statements of reasons for the indication of allowable subject matter:
Regarding claim 5, modified Jo teaches the semiconductor package of claim 1, wherein the dummy die comprises a semiconductor substrate (Jo, para. 86), wherein a direction parallel to a top surface of the semiconductor substrate is defined as a first direction (Jo, x, Fig. 3A), wherein a direction perpendicular to the top surface of the semiconductor substrate is defined as a second direction (Jo, z, Fig. 3A).
Jo does not teach, nor does the prior art of record suggest wherein a magnitude of a height change, in the second direction, of the top surface of the semiconductor substrate toward the first direction is greater than a magnitude of a height change, in the second direction, of a bottom surface of the semiconductor substrate toward the first direction, and wherein the top surface is farther than the bottom surface from the first semiconductor chip.
Ji et al. (US Pub. 20240170458), hereinafter referred to as Ji does teach a semiconductor layer wherein the top surface has a wavelike appearance (Ji, Fig. 3), however, this wavelike portion is in an active semiconductor layer and Ji lacks a dummy die, having only the dummy plate (Ji, 400, Fig. 3) at the top of the stack of semiconductor layers, and the bottom surface of the dummy plate is substantially flat), additionally the wavelike appearance is caused by warpage during assembly (Ji, para. 63) not during the formation process.
Regarding claim 6, modified Jo teaches the semiconductor package of claim 1, wherein the dummy die comprises a semiconductor substrate (Jo, para. 86), but does not teach, nor does the prior art of record suggest wherein the semiconductor substrate comprises a first region and a second region, and wherein a thickness of the first region and a thickness of the second region is different from each other by 0.3 μm or more.
Ji teaches an active semiconductor layer that has a wavelike appearance, but (Ji, Fig. 3), however this is an active layer, and additionally, while the top surface has a wavelike appearance the thickness of the layer appears to be substantially constant along the width. Finally the warpage is caused during the assembly process (Ji, para. 63) not during the formation process.
Regarding claim 8, modified Jo teaches the semiconductor package of claim 7, wherein the first thickness is greater than the third thickness (Jo, paras. 50-51), but does not teach, nor does the prior art of record suggest wherein the first thickness is greater than the second thickness, in fact teaching that it is substantially the same (Jo, para. 89).
Regarding claim 9, modified Jo teaches the semiconductor package of claim 7, but does not teach nor does the prior art of record suggest wherein the second thickness is less than the third thickness. Jo in fact teaches that the second thickness is the same as the first (Jo, para. 89) and that the first is greater than the third (Jo paras. 50-51).
Regarding claim 10, modified Jo teaches the semiconductor package of claim 1, wherein the through-electrodes of the dummy die comprise: a first dummy through-electrode having a first height; and a second dummy through-electrode laterally spaced apart from the first dummy through-electrode and having a second height (Jo, Fig. 3A shows dummy dies 230 having 4 thorough electrodes), but does not teach nor does the prior art of record suggest wherein the first height is greater than the second height.
Regarding claim 11, modified Jo teaches the semiconductor package of claim 1, wherein the through-electrodes of the dummy die comprise:
a first dummy through-electrode (Jo, Fig. 3A, see diagram below); and a second dummy through-electrode laterally spaced apart from the first dummy through-electrode (Jo, Fig. 3A, see diagram below), and wherein a bottom surface of the first dummy through-electrode has substantially the same height as a height of a bottom surface of the second dummy through-electrode (Jo, Fig. 3A, see diagram below).
Modified Jo does not teach, nor does the prior art of record suggest wherein a level of a top surface of the first dummy through-electrode is higher than a level of a top surface of the second dummy through-electrode.
Regarding claim 12, modified Jo teaches the semiconductor package of claim 1, wherein the dummy die comprises: a first dummy through-electrode (Jo, Fig. 3A, see diagram below); a second dummy through-electrode laterally spaced apart from the first dummy through-electrode (Jo, Fig. 3A, see diagram below); a first bonding pad on a bottom surface of the first dummy through-electrode (Jo, Fig. 3A, see diagram below); and a second bonding pad on a bottom surface of the second dummy through-electrode(Jo, Fig. 3A, see diagram below).
Modified Jo does not teach, nor does the prior art of record suggest wherein a first thickness of the first bonding pad is greater than a second thickness of the second bonding pad.
Claim 13 is allowable as depending from allowed claim 12.
Regarding claim 14, modified Jo teaches the semiconductor package of claim 1, wherein the dummy die comprises: a first dummy through-electrode (Jo, Fig. 3A, see diagram below); a second dummy through-electrode laterally spaced apart from the first dummy through-electrode (Jo, Fig. 3A, see diagram below); and a first bonding pad on a bottom surface of the first dummy through-electrode (Jo, Fig. 3A, see diagram below).
Modified Jo does not teach, nor does the prior art of record suggest wherein a level of a bottom surface of the first bonding pad is substantially the same as a level of a bottom surface of the second dummy through-electrode.
Regarding claim 17, modified Jo teaches the semiconductor package of claim 15, wherein the dummy die comprises a semiconductor substrate (Jo, para. 86), wherein a direction parallel to a top surface of the semiconductor substrate is defined as a first direction (Jo, x, Fig. 3A), wherein a direction perpendicular to the top surface of the semiconductor substrate is defined as a second direction (Jo, z, Fig. 3A).
Jo does not teach, nor does the prior art of record suggest wherein a magnitude of a height change, in the second direction, of the top surface of the semiconductor substrate toward the first direction is greater than a magnitude of a height change, in the second direction, of a bottom surface of the semiconductor substrate toward the first direction, and wherein the top surface is farther than the bottom surface from the first semiconductor chip.
Ji et al. (US Pub. 20240170458), hereinafter referred to as Ji does teach a semiconductor layer wherein the top surface has a wavelike appearance (Ji, Fig. 3), however, this wavelike portion is in an active semiconductor layer and Ji lacks a dummy die, having only the dummy plate (Ji, 400, Fig. 3) at the top of the stack of semiconductor layers, and the bottom surface of the dummy plate is substantially flat), additionally the wavelike appearance is caused by warpage during assembly (Ji, para. 63) not during the formation process.
Regarding claim 19, modified Jo teaches the semiconductor package of claim 15, wherein the through-electrodes of the dummy die comprise: a first dummy through-electrode having a first height; and a second dummy through-electrode laterally spaced apart from the first dummy through-electrode and having a second height (Jo, Fig. 3A shows dummy dies 230 having 4 thorough electrodes), but does not teach nor does the prior art of record suggest wherein the first height is greater than the second height.
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jee et al ( US Pub. 20230074933) teaches a semiconductor package with a buffer chip stacked with multiple semiconductor chips wherein the semiconductor chips are enclosed in a molding layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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