DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21, 22, 24, 28 and 29 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hsu et al. (US 9,287,263) hereinafter “Hsu”.
Regarding claim 21, Fig. 11 of Hsu teaches a device comprising: a semiconductor region; a gate stack over the semiconductor region (Item 150), wherein the gate stack comprises: a gate dielectric (Item 104a); and a gate electrode over the gate dielectric, the gate electrode comprising: a first conductive layer (Item 105), wherein the first conductive layers has a U-shape in a cross-section of the gate stack, and wherein the U-shape comprises a horizontal portion and two vertical portions joined to the horizontal portion; a second conductive layer (Item 106) between the first conductive layer and the gate dielectric; and a metallic layer (Item 160a) over and contacting the first conductive layer (Item 105), wherein the metallic layer (Item 106a) comprises a top surface higher than a first topmost surface of the gate dielectric (Item 104a); and a gate spacer (Item 124) on a sidewall of the gate stack, wherein the top surface of the metallic layer (Item 160a) is lower than a second topmost surface of the gate spacer (Item 124).
Regarding claim 22, Fig. 11 of Hsu further teaches where the metallic layer (Item 160a) is a conformal layer (Column 5, Lines 4-5).
Regarding claim 24, Fig. 11 of Hsu further teaches the metallic layer (Item 160a) comprises: a first portion comprising a first bottom surface and a first top surface; and a second portion comprising a second bottom surface higher than the first bottom surface, and a second top surface higher than the first top surface.
Regarding claim 28, Fig. 11 of Hsu further teaches an additional semiconductor region (Item 152); an additional gate spacer (Item 124) over the additional semiconductor region (Item 152); and an additional gate stack, wherein the additional gate spacer is in contact with the additional gate stack, and wherein the additional gate stack comprises: an additional gate dielectric (Not specifically labeled but equivalent to Item 104a); an additional plurality of conductive layers (layers between Items 104 and 164) over the additional gate dielectric; and an additional metallic layer (Item 164) over and contacting the additional plurality of conductive layers, wherein the additional metallic layer is a planar layer (Where the entire top surface of Item 164 is planar).
Regarding claim 29, Fig. 11 of Hsu further teaches where the metallic layer (Item 160a) and the additional metallic layer (Item 164) comprise (See Examiner’s Note below) a same material (Column 4, Lines 48-49 where Item 160 is TiN and Column 5, Lines 58-60 where Item 164 is TiAl such that both Items 160a and 164 comprise a same material, Ti).
Examiner’s Note: The Examiner notes that “comprise a same material” does not require that the layers are the same material, merely that the layers have at least one common material present in the layer. The use of the word comprise denotes that additional materials may be present in the respective layers which may not be common to both layers.
Claims 37 and 39 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Fan et al. (US 2015/0145057) hereinafter “Fan”.
Regarding claim 37, Fig. 20 of Fan teaches a device comprising: a semiconductor region (Rightmost side of the structure); and a gate stack over the semiconductor region, wherein the gate stack comprises: a gate dielectric (Item 118); and a gate electrode over the gate dielectric, the gate electrode comprising: a plurality of conductive layers (Items 120, 124 and 126) comprising a work-function layer (Item 126) therein, wherein a topmost layer (Item 126) of the plurality of conductive layers has a U-shape in a cross-section of the gate stack, and wherein the U-shape comprises a horizontal portion and two vertical portions over and joined to opposing ends of the horizontal portion; and a metallic layer (Item 136; Paragraph 0043 where Item 136 is metallic nitride TiN) over and contacting the plurality of conductive layers, wherein the metallic layer (Item 136) contacts sidewalls of the two vertical portions and a top surface of the horizontal portion of the topmost layer of the plurality of conductive layers, and wherein the metallic layer (Item 136) is in physical contact with the gate dielectric (Item 118).
Regarding claim 39, Fig. 20 of Fan further teaches where the metallic layer (Item 136) is a conformal layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 23, 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (US 2017/0162675) hereinafter “Yim” in view of Liou et al. (US 2016/0284641) hereinafter “Liou”.
Regarding claim 21, Fig. 4M of Yim teaches a device comprising: a semiconductor region; a gate stack over the semiconductor region (Left region of AF), wherein the gate stack comprises: a gate dielectric (Item 410); and a gate electrode over the gate dielectric, the gate electrode comprising: a first conductive layer (Item 422), wherein the first conductive layers has a U-shape in a cross-section of the gate stack, and wherein the U-shape comprises a horizontal portion and two vertical portions joined to the horizontal portion; a second conductive layer (Item 423) between the first conductive layer (Item 422) and the gate dielectric (Item 410); and a metallic layer (Item 430) over and contacting the first conductive layer (Item 422), wherein the metallic layer (Item 430) comprises a top surface higher than a first topmost surface of the gate dielectric (Item 410); and a gate spacer (Item 210) on a sidewall of the gate stack.
Yim does not teach where the top surface of the metallic layer is lower than a second topmost surface of the gate spacer.
Fig. 3 of Liou teaches a gate spacer (Item 24) and a gate electrode (Item 36), where a top surface of the gate electrode (Item 36) is lower than a topmost surface of the gate spacer (Item 24).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the top surface of the metallic layer is lower than a second topmost surface of the gate spacer such that a hard mask is formed directly over the gate electrode, the hard mask protects the gate electrode during the formation of a contact hole such that a contact plug can be formed over and connected to the gate electrode (Liou Paragraph 0026).
Regarding claim 23, Fig. 4M of Yim further teaches where the metallic layer (Item 430) is a planar layer (Where the entire top surface of Item 430 is planar).
Regarding claim 28, Fig. 4M of Yim further teaches an additional semiconductor region (Right region of AF); an additional gate spacer (Item 210) over the additional semiconductor region; and an additional gate stack, wherein the additional gate spacer is in contact with the additional gate stack, and wherein the additional gate stack comprises: an additional gate dielectric (Item 410); an additional plurality of conductive layers (Item 420) over the additional gate dielectric; and an additional metallic layer (Item 430) over and contacting the additional plurality of conductive layers (Item 420), wherein the additional metallic layer is a planar layer (Where the entire top surface of Item 430 is planar).
Regarding claim 29, Fig. 4M of Yim further teaches where the metallic layer and the additional metallic layer (Item 430) comprise a same material.
Claims 30 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 9,287,263) hereinafter “Hsu” in view of Liou et al. (US 2016/0284641) hereinafter “Liou”.
Regarding claim 30, Fig. 11 of Hsu teaches a device comprising: a semiconductor region (Left side); a gate dielectric (Item 104a) over the semiconductor region; a gate electrode over the gate dielectric, the gate electrode comprising: a first conductive layer (Item 105); and a second conductive layer (Item 106) over and electrically connected to the first conductive layer (Item 105); and a metallic layer (Item 160a) over and contacting the second conductive layer (Item 106), wherein a maximum width of the metallic layer (Item 160a) is greater than a maximum vertical length of the metallic layer (Item 160a)
Hsu does not explicitly teach a gate contact plug over and electrically connected to the gate electrode through the metallic layer.
Fig. 3 of Liou teaches a gate electrode (Item 34), where a gate contact plug (Item 50) is over and connected to the gate electrode (Item 34) through a metallic layer (Item 36).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a gate contact plug in the structure of Hsu such that the gate contact plug is over and electrically connected to the gate electrode through the metallic layer because the gate contact plug because the contact plugs allow for electrical connection between a gate structure and other conductive structures on different levels of the device (Liou Paragraph 0022).
Regarding claim 33, Fig. 11 of Hsu further teaches where the metallic layer (Item 160a) is a conformal layer.
Under a different interpretation of Hsu, Claims 30, 31 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 9,287,263) hereinafter “Hsu” in view of Liou et al. (US 2016/0284641) hereinafter “Liou”.
Regarding claim 30, Fig. 11 of Hsu teaches a device comprising: a semiconductor region (Left side); a gate dielectric (Item 104a) over the semiconductor region; a gate electrode over the gate dielectric, the gate electrode comprising: a first conductive layer (Item 105); and a second conductive layer (Item 160a) over and electrically connected to the first conductive layer (Item 105); and a metallic layer (Item 164) over and contacting (electrically) the second conductive layer (Item 160a), wherein a maximum width of the metallic layer (Item 164) is greater than a maximum vertical length of the metallic layer (Item 164)
Hsu does not explicitly teach a gate contact plug over and electrically connected to the gate electrode through the metallic layer.
Fig. 3 of Liou teaches a gate electrode (Item 34), where a gate contact plug (Item 50) is over and connected to the gate electrode (Item 34) through a metallic layer (Item 36).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a gate contact plug in the structure of Hsu such that the gate contact plug is over and electrically connected to the gate electrode through the metallic layer because the gate contact plug because the contact plugs allow for electrical connection between a gate structure and other conductive structures on different levels of the device (Liou Paragraph 0022).
Regarding claim 31, Fig. 11 of Hsu further teaches where the metallic layer (Item 164) has a lower resistivity (Column 5, Lines 58-61) than the first conductive layer (Item 105) and the second conductive layer (Item 163).
Regarding claim 34, Fig. 11 of Hsu further teaches the gate dielectric (Item 104a) comprises a high-k dielectric layer (Column 4, Line 12), and wherein a portion of the high-k dielectric layer (Item 104a) is directly underlying and contacting the second conductive layer (Item 160a).
Alternatively, Claims 30 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (US 2017/0162675) hereinafter “Yim” in view of Liou et al. (US 2016/0284641) hereinafter “Liou”.
Regarding claim 30, Fig. 4M of Yim teaches a device comprising: a semiconductor region; a gate dielectric (Item 410) over the semiconductor region; a gate electrode (Item 420) over the gate dielectric (Item 410), the gate electrode (Item 420) comprising: a first conductive layer (Item 422); and a second conductive layer (Item 423) over and electrically connected to the first conductive layer (Item 422); and a metallic layer (Item 430) over and contacting the second conductive layer (Item 423), wherein a maximum width of the metallic layer (Item 430) is greater than a maximum vertical length of the metallic layer (Item 430).
Yim does not explicitly teach a gate contact plug over and electrically connected to the gate electrode through the metallic layer.
Fig. 3 of Liou teaches a gate electrode (Item 34), where a gate contact plug (Item 50) is over and connected to the gate electrode (Item 34) through a metallic layer (Item 36).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a gate contact plug in the structure of Yim such that the gate contact plug is over and electrically connected to the gate electrode through the metallic layer because the gate contact plug because the contact plugs allow for electrical connection between a gate structure and other conductive structures on different levels of the device (Liou Paragraph 0022).
Regarding claim 32, Fig. 4M of Yim further teaches a gate spacer (Item 210) that comprises a first sidewall contacting a second sidewall of the gate dielectric (Item 410), wherein the metallic layer (Item 430) contacts an upper part of the first sidewall of the gate spacer (Item 210).
Alternatively, Claims 30, 35 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (US 2015/0145057) hereinafter “Fan” in view of Liou et al. (US 2016/0284641) hereinafter “Liou”.
Regarding claim 30, Fig. 20 of Fan teaches a device comprising: a semiconductor region (Rightmost portion of the structure); a gate dielectric (Item 118) over the semiconductor region; a gate electrode over the gate dielectric (Item 118), the gate electrode comprising: a first conductive layer (Item 126); and a second conductive layer (Item 128) over and electrically connected to the first conductive layer (Item 126); and a metallic layer (Item 136; Paragraph 0043 where the Item 136 is a metallic nitride TiN) over and contacting the second conductive layer (Item 128), wherein a maximum width of the metallic layer (Item 136) is greater than a maximum vertical length of the metallic layer (Item 136).
Fan does not explicitly teach a gate contact plug over and electrically connected to the gate electrode through the metallic layer.
Fig. 3 of Liou teaches a gate electrode (Item 34), where a gate contact plug (Item 50) is over and connected to the gate electrode (Item 34) through a metallic layer (Item 36).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a gate contact plug in the structure of Fan such that the gate contact plug is over and electrically connected to the gate electrode through the metallic layer because the gate contact plug because the contact plugs allow for electrical connection between a gate structure and other conductive structures on different levels of the device (Liou Paragraph 0022).
Regarding claim 35, Fig. 20 of Fan further teaches where the gate dielectric (Item 118) comprises a high-k dielectric layer (Paragraph 0032), and wherein the metallic layer (Item 136) contacts a sidewall of the high-k dielectric (Item 118) layer to form a vertical interface.
Regarding claim 36, Fig. 20 of Fan further teaches where an entirety of the second conductive layer (Item 128) is lower than a top end of the high-k dielectric layer (Item 118).
Claims 37 is rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (US 2015/0145057) hereinafter “Yim” in view of Hsu et al. (US 9,287,263) hereinafter “Hsu”.
Regarding claim 37, Fig. 4M of Yim teaches a device comprising: a semiconductor region (Left portion of AF); and a gate stack over the semiconductor region, wherein the gate stack comprises: a gate dielectric (Item 410); and a gate electrode (Item 420) over the gate dielectric (Item 410), the gate electrode (Item 420) comprising: a plurality of conductive layers (Items 421-423) comprising a work-function layer (Paragraph 0035) therein, wherein a topmost layer (Item 423) of the plurality of conductive layers has a U-shape in a cross-section of the gate stack, and wherein the U-shape comprises a horizontal portion and two vertical portions over and joined to opposing ends of the horizontal portion; and a low-resistive conductive layer (Item 430) over and contacting the plurality of conductive layers (Item 421-423), wherein the low-resistive conductive layer (Item 430) contacts sidewalls of the two vertical portions and a top surface of the horizontal portion of the topmost layer (Item 423) of the plurality of conductive layers, and wherein the low-resistive conductive layer (Item 430) is in physical contact with the gate dielectric (Item 410).
Yim does not explicitly teach where the low-resistive conductive layer is a metallic layer.
Fig. 11 of Hsu further teaches where a low-resistive conductive layer (Item 164) has a lower resistivity (Column 5, Lines 58-61) and is a metallic layer (Column 5, Lines 58-61 where the material is Al or TiAl).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the low-resistive conductive layer be a metallic layer because a metallic layer, such as TiAl or Al, is known to exhibit low-resistive properties (Hsu Column 5, Lines 58-61).
Claims 38 is rejected under 35 U.S.C. 103 as being unpatentable over Yim et al. (US 2015/0145057) hereinafter “Fan” in view of Hsu et al. (US 9,287,263) hereinafter “Hsu” and in further view of Liou et al. (US 2016/0284641) hereinafter “Liou”.
Regarding claim 38, the combination of Fan and Hsu teaches all of the elements of the claimed invention as stated above except a gate contact plug over and contacting the metallic layer, wherein the gate contact plug comprises a bottommost surface lower than a topmost end of the gate dielectric.
Fig. 3 of Liou teaches a gate electrode (Item 34), where a gate contact plug (Item 50) is over and contacting a metallic layer (Item 36), where the gate contact plug (Item 50) comprises a bottommost surface lower than a topmost surface of the gate dielectric layer (Not shown but described as being as tall as the gate spacer layer Item 24).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a gate contact plug over and contacting the metallic layer, wherein the gate contact plug comprises a bottommost surface lower than a topmost end of the gate dielectric because the gate contact plug extending to a metallic layer allows for electrical connection between a gate structure and other conductive structures on different levels of the device (Liou Paragraph 0022).
Claim 40 is rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (US 2015/0145057) hereinafter “Fan” in view of Hung et al. (US 2018/0068951) hereinafter “Hung”.
Regarding claim 40, Fan teaches all of the elements of the claimed invention as stated above except a dielectric hard mask over and contacting the metallic layer; and a gate contact plug comprising a first part lower than the dielectric hard mask, and a second part in the dielectric hard mask.
Fig. 7 of Hung teaches a dielectric hard mask (Item 44) over and contacting a gate electrode (Combination of Items 40 and 42); and a gate contact plug (Item 52) comprising a first part lower than the dielectric hard mask (Item 44), and a second part in the dielectric hard mask (Item 44).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a dielectric hard mask over and contacting the metallic layer; and a gate contact plug comprising a first part lower than the dielectric hard mask, and a second part in the dielectric hard mask because this allows the gate contact plug to have better contact with the gate electrode while protecting desired portions of the gate electrode during processing (Hung Paragraph 0003).
Allowable Subject Matter
Claims 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 25, the prior art of record does not teach, suggest or motivate on having ordinary skill in the art to have a dielectric hard mask over and contacting the metallic layer; and a gate contact comprising: a first part physically contacting the first top surface of the first portion of the metallic layer; and a second part in the dielectric hard mask and physically contacting the second top surface of the second portion of the metallic layer along with the scope of claims 21 and 24.
Claims 26 and 27 also include allowable subject matter as they include all of the limitations of claim 25.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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