1Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 16, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pillilli et al. (United States Patent Application Publication US 2020/0175169), hereinafter Pillilli, in view of NASSIF et al. (United States Patent Application Publication US 201801015020), hereinafter NASSIF.
Regarding claim 1, Pillilli teaches a multi-socket computing system, comprising: a master central processing unit (CPU) chip socket; (FIG. 2 “CPU-L” or “CPU-FW” [0016] “FIG. 2 shows a 4-socket server CPU platform with integrated boot enabled.” [0009] “A CPU socket can be a connector to a motherboard or circuit board and that includes a CPU and provides an electrical interface with the CPU.” [0017] “CPU-L or CPU-PW include or use a multiple buffer system to storage at least one segment of a boot code in accordance with embodiments described herein.” Pillilli teaches multi CPU sockets systems. Each CPU socket includes a CPU since a CPU socket is a connector to a motherboard or circuit board and that includes a CPU and provides an electrical interface with the CPU. CPU-L or CPU-FW is interpreted as a master central processing unit (CPU) chip socket.) a slave CPU chip socket; (FIG. 2 “CPU-NL” “CPU-NL,” which includes a CPU, is interpreted as a slave CPU chip socket.)
a first CPU chip disposed in the master CPU socket, the first CPU chip comprising a first CPU; a second CPU chip disposed in the slave CPU socket, the second CPU chip comprising a second CPU; ([0009] “A CPU socket can be a connector to a motherboard or circuit board and that includes a CPU and provides an electrical interface with the CPU.” As discussed above, each CPU socket includes a CPU. A CPU is an integrated circuit. A chip is a physical integrated circuit. Thus, a CPU is interpreted as an integrated circuit or a chip. Furthermore, each CPU socket includes a CPU. Thus, the master CPU socket includes a first CPU, which is in the first CPU chip. Also, the slave CPU socket includes a second CPU chip comprising a second CPU.)
the first CPU configured to: receive a master reset signal indicating at boot-up state; ([0036] “FIG. 4 depicts a process performed by a CPU node at start-up or reboot to fetch boot code. Boot media controller's internal can perform this process. At 402, storage controller performs a boot code command to set up boot media controller buffer.” Since as starting up or booting a CPU-L or a CPU-FW, the CPU must receive a signal to boot or reboot indicating that the CPU starts up or reboot.)
in response to the master reset signal indicating the boot-up state, execute first boot program code to perform a first CPU boot-up operation to: perform a first CPU boot-up task; ([0024] “At 302, a segment number M is initialized.” [0025] “At 304, a prefetch buffer size is set up. CPU-L or CPU-FW BSP BIOS sets up the boot storage controller IP with the prefetch buffer size.” [0026] “At 310, trigger is sent to one or more CPU-NLs to indicate that buffer PBA is available to be read from.” As the CPU-L or CPU-FW starts up or reboots, the CPU-L or the CPU-FW set up a prefetch buffer size for the boot code to be overwritten and the booting procedure from 302-324 as shown in FIG. 3.)
the second CPU configured to, in response to the slave boot-up synchronization signal indicating the boot-up state: execute second boot program code to perform a second CPU boot-up operation comprising a second CPU boot-up task partially concurrent with the performance of the first CPU boot-up operation. ([0031] “At 352, a segment size is received from a boot code agent. For example, a CPU-L or CPU-FW can provide a segment size of N determined in 304.” [0032] “At 354, a trigger to read a retrieval buffer PBA is received. At 356, a CPU-NL reads a segment of boot code from retrieval buffer PBA.” FIG. 3. When the CPU-L or CPU-FW starts booting, the CPU-L or CPU-FW provides a segment size of N and also later transmits a trigger to the CPU-L in order for the CPU-L to perform booting. Furthermore, as shown in FIG. 3, CPU-L performs booting such as initialization of buffers and reading a segment of boot code in response to the segment size of N and a trigger from the CPU-L or the CPU-FW. The booting of the CPU-L is performed in parallel with the CPU-L or the CPU-FW since while the CPU-L or the CPU-FW performs the booting with the boot code in the PBA and the PBB, the CPU-NL also performs the booting.)
However, Pillilli does not explicitly teach in response to the master reset signal indicating the boot-up state, execute first boot program code to perform a first CPU boot-up operation to: set up a sideband communication channel on the sideband communication link; communicate a slave boot-up synchronization signal indicating the boot-up state on the sideband communication channel.
NASSIF teaches in response to the master reset signal indicating the boot-up state, execute first boot program code to perform a first CPU boot-up operation to: set up a sideband communication channel on the sideband communication link; ([0063] “Certain embodiments herein allow dies to influence each other seamlessly and unencumbered with security protection despite die exposure of private sideband messaging between them.” [0144] “Certain interconnects herein support being brought to full functionality up (e.g., very early) in the boot sequence to allow the master die to manage the slave die(s) boot flows (e.g., for the majority of the boot flow),...Certain interconnects herein support a separate physical channel for general purpose sideband messaging” [0150] “FIG. 29 illustrates a flat communication topology 2902 for data exchanges in a multiple die processor 2900 according to embodiments of the disclosure. In the depicted embodiment, topology 2902 represents a flat communication structure that resembles multiple independent processors, as seen in a platform with multiple processor sockets/packages.” [0150] “In the depicted embodiment, topology 2902 represents a flat communication structure that resembles multiple independent processors, as seen in a platform with multiple processor sockets/packages.” [0152] “enabling the interconnect is turning on (e.g., and establishing communication between) a transmitter circuit (e.g., in a first die) and a receiver circuit (e.g., in a second die), for example, one or more instances of receiver circuit(s) and/or one or more instances of transmitter circuit(s) disclosed herein.” Interconnects between master die and the slave die for the communication in the boot sequence using the sideband messaging, which is interpreted as a sideband communication link. Furthermore, the master die manages the slave die boot flows through the sideband messaging. In order for the master die to manage the slave die in the boot flow using the sideband messaging, the master die enables interconnect or sets up the communication using the sideband messaging. Furthermore, NASSIF teaches the communication with multiple processor sockets.)
communicate a slave boot-up synchronization signal indicating the boot-up state on the sideband communication channel. ([0143]” Certain interconnects herein support bidirectional boot handshake signals and/or bidirectional messaging that allow designation of the master die, e.g., after die design, at package assembly, and/or platform assembly. Certain interconnects herein support indication of die status, e.g., to enable both holding messages in back pressure (e.g. credit passing) and/or in long-term lack of readiness to allow auto-responding a message (e.g. not Power OK).” [0144] “Certain interconnects herein support being brought to full functionality up (e.g., very early) in the boot sequence to allow the master die to manage the slave die(s) boot flows (e.g., for the majority of the boot flow),...Certain interconnects herein support a separate physical channel for general purpose sideband messaging” As discussed above, the master die manages the boot flow of the slave die. Thus, the master die sends various commands and indication of die status to the slave die in order to manage boot flows. Also, the communication between dies uses the sideband messaging.)
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pillilli by incorporating the teaching of NASSIF of, in response to the master reset signal indicating the boot-up state, a first CPU boot-up operation to communicate a slave boot-up synchronization signal indicating the boot-up state on the sideband communication channel. They are all directed toward booting multi-processor sockets. The sideband communication can save power, transmit high power signal with less amount of noise. Thus, it would be advantageous to incorporate the teaching of NASSIF of, in response to the master reset signal indicating the boot-up state, a first CPU boot-up operation to communicate a slave boot-up synchronization signal indicating the boot-up state on the sideband communication channel in order to save power, transmit high power signal with less noise.
Regarding claim 2, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
Pillilli, as modified above, further teaches wherein the first CPU boot-up task comprises a first hardware CPU boot-up task ([0010] “BIOS can be firmware executed by a processor to perform hardware initialization during a booting process (e.g., power-on startup), and provide runtime services for operating systems and programs.” [0015] “When a CPU boots (or re-boots), a boot code is loaded and executed by a micro-controller 100. The boot code indicates to allocate at least PBa and PBb in memory 104 ( e.g., data memory). Next, boot controller 102 reads a map of boot code segments to copy to memory 104.” As the CPU boots, the hardware are initialized. Furthermore, buffers in memory 104 are also allocated and mapped during the booting process.).
Regarding claim 3, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
Pillilli, as modified above, further teaches wherein the second hardware CPU boot-up task comprises a second power initialization boot-up task [0010] “BIOS can be firmware executed by a processor to perform hardware initialization during a booting process (e.g., power-on startup), and provide runtime services for operating systems and programs.” The CPU-NL is initialized or booted when power-on.).
Regarding claim(s) 16 and 17, the claim(s) 16 and 17 are the method claims of the apparatus claim(s) 1 and 2. The claim(s) 16 and 17 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Pillilli in view of NASSIF teaches all the limitations of the claim(s) 16 and 17.
Regarding claim(s) 20, the claim(s) 20 are a non-transitory computer-readable medium having stored thereon computer executable instructions claim of the apparatus claim(s) 1. Pillilli further teaches a non-transitory computer-readable medium having stored thereon computer executable instructions ([0064] “computer-readable medium may include a non-transitory storage medium to store or maintain instructions that when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and/or operations in accordance with the described examples.”). The claim(s) 20 does not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Pillilli in view of NASSIF teaches all the limitations of the claim(s) 20.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pillilli in view of NASSIF as applied to claim 1 above, and further in view of KIM HYOUNG SU (KF 20140099016 A), hereinafter KIM.
Regarding claim 4, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
NASSIF further teaches a clock circuit coupled to the master CPU socket and the slave CPU socket and configured to provide a clock signal to the first CPU chip and the second CPU chip ([0075] “The first die may be operating at an operating frequency and the second die may be operating at an (e.g., the same) operating frequency, but a clock circuit ( e.g., clock circuit 408) may adjust the clock phase placement for the operating frequency (e.g., and a clocking rate for the operating frequency) from a plurality of clock phase placements (e.g., for the same clock cycle).”).
However, Pillilli in view of NASSIF does not explicitly teach wherein the second hardware CPU boot-up task is configured to initialize the clock circuit.
KIM teaches wherein the second hardware CPU boot-up task is configured to initialize the clock circuit (Page 3 “The control unit 30 may be implemented by a CPU or a main decoder IC.” Page 4 “the control unit 30 supplies the main clock signal to the clock branching unit 10 after a predetermined time has elapsed after power is applied and the clock branching unit 10 and the storage unit 20 can be stabilized.” KIM teaches booting process. During the booting process, the control unit, which is implemented by a CPU, supplies clock signal.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pillilli in view of NASSIF by incorporating the teaching of KIM of wherein the second hardware CPU boot-up task is configured to initialize the clock circuit. They are all directed toward booting process. A clock signal is one of the most essential components for synchronization, and timing. Thus, it is obvious to initialize a circuit to supply the clock signal during the booting process especially when the clock signal is the most essential component of the computer system. Therefore, it would be obvious to incorporate the teaching of KIM of wherein the second hardware CPU boot-up task is configured to initialize the clock circuit.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pillilli in view of NASSIF as applied to claim 1 above, and further in view of Lambert et al. (United States Patent Application Publication US 2021/0081214), hereinafter Lambert.
Regarding claim 5, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
Pillilli, as modified above, further teaches a power rail coupled to the master CPU socket and the slave CPU socket and configured to provide a voltage to the first CPU chip and the second CPU chip ([0054] “A power source (not depicted) provides power to the components of system 500. More specifically, power source typically interfaces to one or multiple power supplies in system 500 to provide power to the components of system 500.”).
However, Pillilli in view of NASSIF does not explicitly teach wherein the second hardware CPU boot-up task is configured to initialize a voltage level of the voltage of the power rail.
Lambert teaches wherein the second hardware CPU boot-up task is configured to initialize a voltage level of the voltage of the power rail ([0035] “the CPLD 214, after placing each socket 202 in the auxiliary power state, alters parameters associated with the sockets 202.” [0036] “altering the parameters associated with the sockets 202 can include the CPLD 214 altering the CPU straps, power sequencing, reset sequencing, serial peripheral interface (SPI) multiplexing, and/or the bus direction associated with the sockets 202.” A power sequencing is an order or sequence to control the power supply. Especially, the power sequencing during the booting process is to start or initialize the power or voltage.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pillilli in view of NASSIF by incorporating the teaching of Lambert to initialize a voltage level of the voltage of the power rail. As the system includes multiple components, the control of the power supply to various components to avoid unintentional application of power, which can cause damages to the components. Therefore, it would be advantageous to incorporate the teaching of Lambert to initialize a voltage level of the voltage of the power rail in order to avoid unintentional damages to the system.
Claim(s) 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pillilli in view of NASSIF as applied to claims 1 and 16 above, and further in view of KHESSIB et al. (United States Patent Application Publication US 2019/0073478), hereinafter KHESSIB.
Regarding claim 6, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
However, Pillilli in view of NASSIF does not explicitly teach a second memory comprising at least one second memory chip coupled to the slave CPU socket; wherein the second hardware CPU boot-up task is configured to initialize the at least one second memory chip.
KHESSIB teaches a second memory comprising at least one second memory chip coupled to the slave CPU socket (FIG. 1 “150” “160” “Memory 180” [0028] “Memory 180 may comprise one or more flash memory devices…” [0029] “Memory 180 may comprise to any memory device having a common communication interface with RoT.”);
wherein the second hardware CPU boot-up task is configured to initialize the at least one second memory chip (FIG. 2 “Energize All Power Rails Of Peripheral Component And Allow CPU To Boot S208” Peripheral component includes a memory 180, which is coupled to the slave CPU socket as shown in FIG. 1. As the peripheral component is energized during the boot process, the memory is also energized and initialized.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pillilli in view of NASSIF by incorporating the teaching of KHESSIB of a second memory comprising at least one second memory chip coupled to the slave CPU socket; wherein the second hardware CPU boot-up task is configured to initialize the at least one second memory chip. They are all directed toward booting process. Since the booting process is to initialize hardware, it is obvious to boot by energizing the memory coupled to the slave CPU in order to initialize the memory coupled to the slave CPU.
Regarding claim(s) 18, the claim(s) 18 is the method claim of the apparatus claim(s) 6. The claim(s) 18 does not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Pillilli in view of NASSIF and further in view of KHESSIB teaches all the limitations of the claim(s) 18.
Claim(s) 7, 9, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pillilli in view of NASSIF as applied to claims 1 and 16 above, and further in view of Collins (United States Patent US 6158000), hereinafter Collins.
Regarding claim 7, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
Pillilli, as modified above, further teaches a system memory, comprising: a first memory comprising at least one first memory chip; and the first CPU configured to perform the first CPU boot-up task comprising initializing a respective first memory chip among the at least one first memory chip (FIG. 1 “Data Memory 101” “Storage” [0013] [0012] “Boot code storage 110 can store boot code, in some examples.” [0013] “Memory 104 can be a memory device and buffers PBa and PBb are allocated in the memory device (e.g., by execution of a boot code).” Pillilli teaches booting process, which is performed using the boot code and buffers in the memory device. Thus, Pillilli suggests that the memory devices are initialized during the booting process.).
However, Pillilli in view of NASSIF does not explicitly teach a second memory comprising at least one second memory chip; and the second CPU configured to execute the second boot program code to perform the second CPU boot-up operation comprising the second hardware CPU boot-up task comprising initializing a respective second memory chip among the at least one second memory chip.
Collins teaches a second memory comprising at least one second memory chip; and the second CPU configured to execute the second boot program code to perform the second CPU boot-up operation comprising the second hardware CPU boot-up task comprising initializing a respective second memory chip among the at least one second memory chip ([Col. 5 Lines 54-57] “Initialization of computer system 100 preferably includes performing a sequence of tasks. This task sequence may begin with causing every system component to enter an initial state at power-on.” [Col. 8 Lines 20-25] “if a multiple processor environment is detected, then in step 325 the ESP may send an IPI to the other APs to have them conduct local tasks (e.g. tests of the processor registers and cache memory belonging to each AP” As the other application processors boot while the BSP controls a boot process, such as POST tasks during the boot process, the other APs tests of the processor registers and cache memory belonging to each AP, which is a process of the initializing the memory device.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pillilli in view of NASSIF by incorporating the teaching of Collins of a second memory comprising at least one second memory chip; and the second CPU configured to execute the second boot program code to perform the second CPU boot-up operation comprising the second hardware CPU boot-up task comprising initializing a respective second memory chip among the at least one second memory chip. They are all directed toward booting process. As recognized by Collins, in many systems, particularly those performing critical roles it is desirable to reduce boot-up time without sacrificing the assurance provided by performing the POST on a regular basis (Col. 3 Lines 36-39). By initializing a second memory coupled to the second processor by conducting local tasks of the APs, the booting process, such as POST can be reduced. Therefore, it would be advantageous to incorporate the teaching of Collins of a second memory comprising at least one second memory chip; and the second CPU configured to execute the second boot program code to perform the second CPU boot-up operation comprising the second hardware CPU boot-up task comprising initializing a respective second memory chip among the at least one second memory chip in order to reduce the booting time.
Regarding claim 9, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
Pillilli teaches a reset port configured to receive the master reset signal; the master CPU socket is coupled to the reset port.
Collins further teaches the slave CPU socket is coupled to the reset port; the second CPU configured to, in response to the master reset signal indicating the boot-up state and the slave boot-up synchronization signal indicating the boot-up state (Col. 7 Lines 1-2, “In response to the reset signal, the system processors 110-113 enter an initial state in step 306.”):
execute the second boot program code to initiate the second CPU boot-up operation to perform the second hardware CPU boot-up task partially concurrent with the performance of the first CPU boot-up operation ([Col. 8 Lines 20-25] “if a multiple processor environment is detected, then in step 325 the ESP may send an IPI to the other APs to have them conduct local tasks (e.g. tests of the processor registers and cache memory belonging to each AP) In step 326 the BSP instructs an AP to start performing the memory test.”).
Regarding claim(s) 19, the claim(s) 19 is the method claim of the apparatus claim(s) 7. The claim(s) 19 does not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Pillilli in view of NASSIF and further in view of Collins teaches all the limitations of the claim(s) 19.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pillilli in view of NASSIF as applied to claim 1 above, and further in view of Hsien (United States Patent Application Publication US 2013/0145166), hereinafter Hsien.
Regarding claim 10, Pillilli in view of NASSIF teaches all the limitations of the multi-socket computing system of claim 1, as discussed above.
NASSIF teaches the sideband communication channel ([0063] “Certain embodiments herein allow dies to influence each other seamlessly and unencumbered with security protection despite die exposure of private sideband messaging between them.”).
However, Pillilli in view of NASSIF does not explicitly teach the first CPU is configured to perform the first CPU boot-up operation by being further configured to: receive the second CPU identification on the communication channel; and determine if the second CPU is valid based on authentication of the second CPU.
Hsien teaches the first CPU is configured to perform the first CPU boot-up operation by being further configured to: receive the second CPU identification on the communication channel ([0022] “The method starts with generating authentication data 148 according to data to be transmitted 142 and identification data 112 corresponding to authorized receiving processor (S200). The first processor 110 may obtain the identification data 112 during manufacturing stage or retrieve from the authorized processor in advance, for example the second processor 120 in this embodiment.”); and
determine if the second CPU is valid based on authentication of the second CPU ([0023] “Upon receiving the data 142 and the authentication data 148, the second processor 120 performs authentication according to the authentication data 148 and identification data 122 of its own as shown in step S220. The authentication data 148 can be confirmed if the identification data 122 of the second processor 120 matches the identification data 112 used for generating the authentication data 148. In response to the authentication data 148 is confirmed, the second processor 120 may access data 142 and perform operation corresponding to the data 142.” Based on the identification data or authentication data, the second CPU is authenticated.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pillilli in view of NASSIF by incorporating the teaching of Hsien of the first CPU configured to perform the first CPU boot-up operation by being further configured to: receive the second CPU identification on the communication channel; and determine if the second CPU is valid based on authentication of the second CPU. They are all directed toward the booting process. As recognized by Hsien, the electronic device of the prior art does not have any authentication mechanism to effectively prevent the data transmitted between processors from being monitored or changed ([0005]). By authenticating the second processor using the identification data, the security of the system can be improved. Therefore, it would be advantageous to incorporate the teaching of Hsien of the first CPU configured to perform the first CPU boot-up operation by being further configured to: receive the second CPU identification on the communication channel; and determine if the second CPU is valid based on authentication of the second CPU in order to improve the security of the system.
Claim(s) 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Pillilli in view of NASSIF and further in view of Hsien as applied to claim 10 above, and further in view of KHESSIB.
Regarding claim 11, Pillilli in view of NASSIF and further in view of Hsien teaches all the limitations of the multi-socket computing system of claim 10, as discussed above.
However, Pillilli in view of NASSIF and further in view of Hsien does not explicitly teach wherein the first CPU is further configured to, in response to determining the second CPU is not valid, perform the first CPU boot-up task in a standalone mode.
KHESSIB teaches wherein the first CPU is further configured to, in response to determining the second CPU is not valid, perform the first CPU boot-up task in a standalone mode ([0058] “If it is determined at S480 that the peripheral firmware has not been authenticated (either because no authentication measurement is received from RoT 370, or because a received authentication measurement indicates that the firmware could not be authenticated),…based on platform policies, CPU 310 is allowed to come out of reset and boot at S490, but full power is not applied to peripheral component card 305.” As the slave is not authenticated, the CPU 310, which is the master, still come out of reset and boot, which is executing alone.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pillilli in view of NASSIF and further in view of Hsien by incorporating the teaching of KHESSIB of wherein the first CPU is further configured to, in response to determining the second CPU is not valid, perform the first CPU boot-up task in a standalone mode. While the second CPU is not authenticated, which is not in fully functioning, the first or master CPU boots and performs function, which allows the system to function and reduce the downtime. Therefore, it would be advantageous to incorporate the teaching of KHESSIB of wherein the first CPU is further configured to, in response to determining the second CPU is not valid, perform the first CPU boot-up task in a standalone mode in order to reduce the downtime.
Regarding claim 12, Pillilli in view of NASSIF and further in view of Hsien teaches all the limitations of the multi-socket computing system of claim 10, as discussed above.
KHESSIB further teaches wherein the first CPU is further configured to, in response to determining the second CPU is not valid, discontinue performance of the first CPU boot-up task ([0058] “If it is determined at S480 that the peripheral firmware has not been authenticated ( either because no authentication measurement is received from RoT 370, or because a received authentication measurement indicates that the firmware could not be authenticated), the boot process is terminated at S490…” As the boot process is terminated, the CPU 310 or the first CPU also terminates the boot process).
Regarding claim 13, Pillilli in view of NASSIF and further in view of Hsien teaches all the limitations of the multi-socket computing system of claim 10, as discussed above.
KHESSIB further teaches wherein the first CPU is further configured to, in response to determining the second CPU is valid, continue performance of the first CPU boot-up task ([0057] “Flow proceeds from S480 to S485 if the peripheral firmware has been successfully authenticated. At S285, all power rails of the peripheral component card are energized, allowing SoC 360 to boot the firmware of memory 380. CPU 310 is also taken out of reset and allowed to boot the firmware of memory 330. The power sequencing and signaling may be performed by RoT 320 in coordination with a CPLD mounted on motherboard 300.”).
Regarding claim 14, Pillilli in view of NASSIF and further in view of Hsien teaches all the limitations of the multi-socket computing system of claim 10, as discussed above.
NASSIF teaches the sideband communication ([0063] “Certain embodiments herein allow dies to influence each other seamlessly and unencumbered with security protection despite die exposure of private sideband messaging between them.”).
Hsien teaches the second CPU identification ([0022] “The method starts with generating authentication data 148 according to data to be transmitted 142 and identification data 112 corresponding to authorized receiving processor (S200). The first processor 110 may obtain the identification data 112 during manufacturing stage or retrieve from the authorized processor in advance, for example the second processor 120 in this embodiment.”).
KHESSIB further teaches wherein the first CPU is configured to perform the first CPU boot-up operation by being further configured to: determine if the second CPU information on the communication channel has not been received within a predetermined authentication time; and in response to the second CPU information not being received within the predetermined authentication time, identify the slave CPU socket as not authentic ([0058] “If it is determined at S480 that the peripheral firmware has not been authenticated (either because no authentication measurement is received from RoT 370, or because a received authentication measurement indicates that the firmware could not be authenticated)” In order to determine that the authentication measurement has not been received, KHESSIB suggests that determination to receive the authentication measurement is made within a predetermined since the determination cannot be waiting limitlessly.).
Allowable Subject Matter
Claims 8 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Pillilli teaches that a CPU sockets provides coordination such that one or more CPU sockets have copied a boot code segment in the buffer before permitting the segment to be overwritten in the buffer. However, Pilli does not teach “the first CPU is further configured to determine a memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip; and the second CPU is further configured to determine the memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip” and “wherein the first CPU is configured to perform the first CPU boot-up task by being configured to set up a high-speed sideband communication channel on the sideband communication link having a bandwidth greater than the sideband communication channel.”
NASSIF teaches sideband communication channel between plurality of physically separate dies. However, NASSIF does not teach “the first CPU is further configured to determine a memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip; and the second CPU is further configured to determine the memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip” and “wherein the first CPU is configured to perform the first CPU boot-up task by being configured to set up a high-speed sideband communication channel on the sideband communication link having a bandwidth greater than the sideband communication channel.”
Lambert teaches switching a mode of an information handling system between a multi-single socket mode and a multi-socket mode. However, Lambert does not teach “the first CPU is further configured to determine a memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip; and the second CPU is further configured to determine the memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip” and “wherein the first CPU is configured to perform the first CPU boot-up task by being configured to set up a high-speed sideband communication channel on the sideband communication link having a bandwidth greater than the sideband communication channel.”
KHESSIB teaches authenticating a peripheral component during a booting process. However, KHESSIB does not teach “the first CPU is further configured to determine a memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip; and the second CPU is further configured to determine the memory map for the system memory based on the initialization of the at least one first memory chip and the at least one second memory chip” and “wherein the first CPU is configured to perform the first CPU boot-up task by being configured to set up a high-speed sideband communication channel on the sideband communication link having a bandwidth greater than the sideband communication channel.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
DAS et al. (United States Patent Application Publication US 2016/0004542) teaches initializing at least two CPUs of multiple CPUs to perform task in parallel.
Roh et al. (United States Patent Application Publication US 2007/0192529) teaches a boot memory including a plurality of boot codes to initialize a plurality of intellectual property blocks.
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/HYUN SOO KIM/Examiner, Art Unit 2176