Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to application filed on 10/2/24.
Information Disclosure Statement (IDS) filed on 4/15/25.
Claims 1-20 are presented for examination.
Claims 1-20 are pending.
Double Patent Rejection
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claim of U.S. Patent No. 12/087345 and US Patent No. 11,195,567. Although the conflicting claims are not identical, they are not patentably distinct from each other because of the reasons set forth below.
Claim 1-20 are rejected in view of claim of the “345 patent and ‘567. Similar to the claimed invention, claim 1-20 of the patents recites a “A device comprising: a first transistor switch connected to a near-end of a bit line; a second transistor switch connected to a far-end of the bit line, wherein the first transistor switch and second transistor switch are responsive to a pass signal; a Metal Oxide Semiconductor (MOS) capacitor and a metal capacitor connected in parallel, the MOS capacitor connected directly to one of the first transistor switch and the second transistor switch and the metal capacitor being directly connected to the first transistor switch or second transistor switch not connected to the MOS capacitor; and a control circuit configured to output a kick signal falling from a ground level to a negative level, wherein the kick signal is applied to both the MOS capacitor and the metal capacitor.” and “A write assist circuit, comprising: a bit line BL having a near-end and a far-end; a first switch transistor connected to the near-end of the bit line BL; a second switch transistor connected to the far-end of the bit line; a first capacitor connected to the first switch transistor; a first middle end capacitor connected to the near-end of the bit line BL and in parallel to the first capacitor; a second capacitor connected to the second switch transistor, wherein the second capacitor is connected in parallel to the first capacitor, and wherein the first capacitor and second capacitor maintain a balanced negative voltage to the near-end and far- end for a period of time during a write enable signal, and “A write assist circuit, comprising: a bit line BL having a near-end and a far-end; a first switch transistor connected to the near-end of the bit line BL; a second switch transistor connected to the far-end of the bit line; a first capacitor connected to the first switch transistor; a second capacitor connected to the second switch transistor, wherein the second capacitor is connected in parallel to the first capacitor; a first middle end capacitor connected to the far-end of the bit line and in parallel to the second capacitor, and wherein the first capacitor and second capacitor maintain a balanced negative voltage to the near-end and far-end during a write enable signal”.
As can be seen, the patent protection for the claimed invention has already been granted to the earlier filed application.
eTerminal Disclaimer
The USPT© internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 would be allowable if an eTerminal Disclaimer signed and filed by an attorney or agent of record to overcome the obviousness-type double patenting rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants' disclosure. Liu et al (US 12,362,000) discloses a memory device with memory cells and associated circuitry that controls and applies voltages to the memory structure, including dynamic voltage adjustment, using controllable elements (e.g. capacitors and switching responsive to signals). However, Liu does not teach: a bias memory cell coupled to a memory cell, a multi-gate electrodes and does not provide current-based control via a drain electrode. Instead, Liu relies on capacitive switching with kick signals, rather than the bias memory cell-based regulation required by the instant application.
When responding to the office action, Applicants' are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Connie Yoha, whose telephone number is (571) 272-1799. The examiner can normally be reached on Mon. - Fri. from 8:00 A.M. to 5:30 PM. The examiner's supervisor, Alexander Sofocleous, can be reached at (571) 272-0635. The fax phone number for this Group is (571) 273-8300.
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/CONNIE C YOHA/ Primary Examiner, Art Unit 2825
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