Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 7/15/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
EXAMINER'S AMENDMENT
3. An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
Authorization for this examiner’s amendment was given in an interview with Ronald Neerings on 4/14/26.
The application has been amended as follows:
Initial claims 1-20 remains as is. Claims 12-16 (repeat) following claim 20 has been cancelled.
12. (Cancelled)
13. (Cancelled)
14. (Cancelled)
15. (Cancelled)
16. (Cancelled)
Claim Status
4. Claims 1-20 are pending in the application. Second set of (repeat) claims 12-16 are cancelled.
Claim Objections
5. Claim 20 is objected to because of the following informalities: claim 20 dependency on itself needs to be corrected, it will be treated as if it depends on claim 10. Appropriate correction is required.
Double Patenting
6. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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7. Claims 1-9 and 10-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 and 17-20 of U.S. Patent No. 12,044,719 (hereinafter “Hubbard719”). Although the claims at issue are not identical, they are not patentably distinct from each other because both sets of claims cover the same subject matter, see mapping below
8. Regarding claim 1, A probe card comprising: a voltage terminal configured to be coupled to a voltage supply; a current terminal configured to be coupled to a current supply, wherein the voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles; and a overlap resistor capacitor (RC) element coupled to the input node of the DUT FET and to an electrically neutral node [Hubbard719, Claim 1, lines 1-11].
9. Regarding claim 2, further including an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles [Hubbard719, Claim 1, lines 12-15].
10. Regarding claim 3, further including a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node [Hubbard719, Claim 1, lines 16-18].
11. Regarding claim 4, further including an ADC current capture module coupled in parallel to the resistive element [Hubbard719, Claim 1, lines 19-20].
12. Regarding claim 5, wherein the DUT FET is embedded in a wafer [Hubbard719, Claim 2].
13. Regarding claim 6, wherein the DUT FET is a gallium nitride (GaN) FET [Hubbard719, Claim 3].
14. Regarding claim 7, wherein the ADC voltage capture module is configured to capture at least 20 million voltage measurements per second and the ADC current capture module is configured to capture at least 50 million current measurements per second [Hubbard719, Claim 4].
15. Regarding claim 8, wherein the ADC voltage capture module and the ADC current capture module are configured to provide data to a data acquisition system of an automatic test equipment (ATE) to measure a drain to source on resistance of the DUT FET [Hubbard719, Claim 5].
16. Regarding claim 9, wherein the ATE further comprises: an ATE head; a prober interface board (PIB) mounted on the ATE head, the PIB comprising the voltage supply and the current supply, wherein the probe card is mounted on the PIB, and the probe card overlies the wafer [Hubbard719, Claim 6].
17. Regarding claim 10, A method for testing a device under test (DUT), the method comprising: coupling probe needles extending from a probe card to an input port, an output port and a gate of a DUT field effect transistor (FET), wherein the DUT FET is embedded in a wafer; and applying a direct current (DC) voltage to an input node of the DUT FET and to an overlap resistor capacitor (RC) element to charge the RC element [Hubbard719, Claim 17, lines 1-9].
18. Regarding claim 11, further including switching the DUT FET between a cutoff region and a linear region by applying a time varying signal to a gate of the DUT FET, wherein current is injected into the input node of the DUT FET from the overlap RC element and voltage is applied to the input node of the DUT FET during time intervals that the DUT FET switches from the cutoff region to the linear region [Hubbard719, Claim 17, lines 10-16].
19. Regarding claim 12, further including injecting a DC current to the input node of the DUT FET in response to depletion of the current injected by the overlap RC element during an interval of time the DUT FET is operating in the linear region. [Hubbard719, Claim 17, lines 17-20].
20. Regarding claim 13, further including measuring, by an analog to digital (ADC) voltage capture module of the probe card, a voltage between an input node and an output node of the DUT FET during the switching of the DUT FET [Hubbard719, Claim 17, lines 21-24].
21. Regarding claim 14, further including measuring, by an ADC current capture module of the probe card, coupled in parallel to a resistive element coupled to the output node of the DUT FET and an electrically neutral node, a current through the resistive element during the switching of the DUT FET [Hubbard719, Claim 17, lines 25-29].
22. Regarding claim 15, further comprising: repeating the switching of the DUT FET at least fifty times; and determining whether a drain to source on resistance of the DUT FET exceeds a threshold for one or more of the switches of the DUT FET [Hubbard719, Claim 18].
23. Regarding claim 16, further comprising: repeating the switching of the DUT FET at least fifty times; and determining whether a drain to source on resistance of the DUT FET increases as a function of a number of switches at a rate that exceeds a threshold [Hubbard719, Claim 19].
24. Regarding claim 17, wherein the DUT is a gallium nitride (GaN) FET [Hubbard719, Claim 20].
25. Regarding claim 18, further comprising: repeating the switching of the DUT FET at least fifty times; and determining whether a drain to source on resistance of the DUT FET exceeds a threshold for one or more of the switches of the DUT FET [Hubbard719, Claim 18].
26. Regarding claim 19, further comprising: repeating the switching of the DUT FET at least fifty times; and determining whether a drain to source on resistance of the DUT FET increases as a function of a number of switches at a rate that exceeds a threshold [Hubbard719, Claim 19].
27. Regarding claim 20, wherein the DUT is a gallium nitride (GaN) FET [Hubbard719, Claim 20].
Note: claim 10 is rejected twice below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
28. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
29. Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Weimer (US 2015/0276803).
30. Regarding claim 1, Weimer teaches A probe card [Figures 1-7, a probe card is shown] comprising: a voltage terminal configured to be coupled to a voltage supply [Figures 1-7, a voltage terminal configured to be coupled to a voltage supply 242 is shown]; a current terminal configured to be coupled to a current supply, wherein the voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles [Figures 1-7, a current terminal coupled to a current supply 246, the voltage terminal and the current terminal are coupled to an input node of a DUT FET 180 through probe needles (input node) 148]; and a overlap resistor capacitor (RC) element coupled to the input node of the DUT FET and to an electrically neutral node [Figures 1-7, a RC element 322, 324 coupled to the input node of the DUT FET 180 and to ground or electrically neutral node is shown; see Figure 5, wire 152/158 is connected to node 148].
31. Regarding claim 5, Weimer teaches wherein the DUT FET is embedded in a wafer [Figures 1-7, the DUT FET 180 is embedded in a wafer 160].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
31. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
32. Claims 2-4, 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Weimer (US 2015/0276803) in view of Tadepalli et al. (US 2021/0080498). (“Tadepalli”)
33. Regarding claim 2, Weimer teaches the probe card.
Weimer does not explicitly teach further including an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles.
However, Tadepalli teaches further including an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles [Figures 1-4, 15 teaches an ADC 1510 to be coupled to the DUT FET 130].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Tadepalli. Doing so would allow Weimer to comprise an ADC coupled to the DUT which would help with data processing.
34. Regarding claim 3, Weimer teaches further including a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node [Figures 1-7, see resistive element 510].
35. Regarding claim 4, Weimer teaches the probe card.
Weimer does not explicitly teach further including an ADC current capture module coupled in parallel to the resistive element.
However, Tadepalli teaches further including an ADC current capture module coupled in parallel to the resistive element [Figures 1-4, 15 teaches an ADC current capture module 1510 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Tadepalli. Doing so would allow Weimer to comprise an ADC current capture module which would help with data processing.
36. Regarding claim 6, Weimer teaches the probe card.
Weimer does not explicitly teach wherein the DUT FET is a gallium nitride (GaN) FET.
However, Tadepalli teaches wherein the DUT FET is a gallium nitride (GaN) FET [Figures 1-4, P(0025, 0030) teaches GaN FET].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Tadepalli. Doing so would allow Weimer to transistor formed of GaN material which would help improve life span of the material.
37. Regarding claim 7, Weimer teaches the probe card.
Weimer does not explicitly teach wherein the ADC voltage capture module is configured to capture at least 20 million voltage measurements per second and the ADC current capture module is configured to capture at least 50 million current measurements per second.
However, Tadepalli teaches ADC voltage capture module [Figures 1-4, 15 teaches the ADC voltage capture 1510].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Tadepalli. Doing so would allow Weimer to comprise an ADC coupled to the DUT which would help with data processing.
Weimer and Tadepalli does not explicitly teach wherein the ADC voltage capture module is configured to capture at least 20 million voltage measurements per second and the ADC current capture module is configured to capture at least 50 million current measurements per second.
However, it would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer and Tadepalli to optimize the measurement value per second because it has been held that “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). (MPEP 2144.05).
38. Regarding claim 8, Weimer teaches the probe card.
Weimer does not explicitly teach wherein the ADC voltage capture module and the ADC current capture module are configured to provide data to a data acquisition system of an automatic test equipment (ATE) to measure a drain to source on resistance of the DUT FET.
However, Tadepalli teaches wherein the ADC voltage capture module and the ADC current capture module are configured to provide data to a data acquisition system of an automatic test equipment (ATE) to measure a drain to source on resistance of the DUT FET [Figures 1-4, 15 teaches an ADC voltage and current capture module 1510 is shown].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Tadepalli. Doing so would allow Weimer to comprise an ADC voltage and current capture module which would help with data processing.
39. Regarding claim 9, Weimer teaches wherein the ATE further comprises: an ATE head; a prober interface board (PIB) mounted on the ATE head, the PIB comprising the voltage supply and the current supply, wherein the probe card is mounted on the PIB, and the probe card overlies the wafer [Figures 1-7, the ATE 100/110 is shown, PIB 116 is shown comprising the voltage supply, the current supply and the probe card 118 is shown].
40. Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Weimer (US 2015/0276803) in view of Tadepalli et al. (US 2021/0080498).
41. Regarding claim 10, Weimer teaches A method for testing a device under test (DUT) [Figures 1-7, a method for testing a DUT 180 is taught], the method comprising: coupling probe needles extending from a probe card to an input port, an output port and a gate of a DUT field effect transistor (FET), wherein the DUT FET is embedded in a wafer [Figures 1-7, probe needles 148/152 are coupled extending from a probe card 118 to an input node, an output node and gate of the DUT FET 180, the DUT FET 180 is embedded in a wafer 160]; and applying a (direct current (DC)) voltage to an input node of the DUT FET and to an overlap resistor capacitor (RC) element to charge the RC element [Figures 1-7, applying a voltage 242 to an input node of the DUT FET 180 and to an overlap resistor capacitor element 322, 324].
Weimer does not explicitly teach a direct current (DC) voltage.
However, Tadepalli teaches a direct current (DC) voltage [Figures 1-4, see DC voltage source 102].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Tadepalli. Doing so would allow the system to obtain stable power which would help improve testing.
42. Regarding claim 20, Weimer teaches the method.
Weimer does not explicitly teach wherein the DUT is a gallium nitride (GaN) FET.
However, Tadepalli teaches wherein the DUT is a gallium nitride (GaN) FET [Figures 1-4, P(0025, 0030) teaches GaN FET].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Tadepalli. Doing so would allow Weimer to transistor formed of GaN material which would help improve life span of the material.
wherein the DUT is a gallium nitride (GaN) FET.
43. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weimer (US 2015/0276803) in view of Domingo et al. (US 2013/0278300). (“Domingo”).
44. Regarding claim 10, Weimer teaches A method for testing a device under test (DUT) [Figures 1-7, a method for testing a DUT 180 is taught], the method comprising: coupling probe needles extending from a probe card to an input port, an output port and a gate of a DUT field effect transistor (FET), wherein the DUT FET is embedded in a wafer [Figures 1-7, probe needles 148/152 are coupled extending from a probe card 118 to an input node, an output node and gate of the DUT FET 180, the DUT FET 180 is embedded in a wafer 160]; and applying a (direct current (DC)) voltage to an input node of the DUT FET and to an overlap resistor capacitor (RC) element to charge the RC element [Figures 1-7, applying a voltage 242 to an input node of the DUT FET 180 and to an overlap resistor capacitor element 322, 324].
Weimer does not explicitly teach a direct current (DC) voltage.
However, Domingo teaches a direct current (DC) voltage [Figure 4, see DC voltage source 204].
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Weimer with Domingo. Doing so would allow the system to obtain stable power which would help improve testing.
Note: no prior art rejection is made for claims 11-19, they stand rejected under double patenting.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Elridge et al. (US 2002/0186037), Figure 5 shows a power supply for an IC under test, comprising power supply, probe card, tester, DUT, resistor and capacitor and so on.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEEL D SHAH whose telephone number is (571)270-3766. The examiner can normally be reached M-F: 9AM-5:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NEEL D SHAH/ Primary Examiner, Art Unit 2858
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