Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ismail et al. (US Pub # 2021/0406118) in view of Lien (US Pub # 2017/0090764).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Ismail et al. teach a method of improving a performance of a non-volatile memory, comprising: generating, based on a number of program erase cycles of the non-volatile memory, an inversion seed for a page type of the non-volatile memory; generating a circular shift flip sequence based on the inversion seed and a flip sequence (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139, 0151, data sequence in circular shift register, inversion seed in Fig. 4B); performing a bit-flipping operation on an input bit sequence based on the circular shift flip sequence to generate an intermediate bit sequence; processing the intermediate bit sequence to generate an output bit sequence; and writing the output bit sequence to a page in the non-volatile memory, wherein the page is of the page type (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139, 0151, bit flipping in step 4029, write operation in step 403, output sequence read from memory).
Even though Ismail et al. teach program / erase cycle (see paragraph 0003) but silent exclusively about generating, based on a number of program erase cycles of the non-volatile memory.
Lien teaches generating, based on a number of program erase cycles of the non-volatile memory (see Fig. 7-8, paragraph 0046-0058 where data sequence generated from PE input including address).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lien to the teaching of Ismail et al. where computing device 100 of Ismail et al. would be considered as data sequencer 150 taught by Lien and to generate bit sequence in order to yield improved cell distributions and to extend useful life of memory device (see Lien, paragraph 0025, 0067).
Further reason to combine the teachings of Lien and Ismail et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards error correction of flash memory array.
Regarding claim 2, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ismail et al. further teach, wherein processing the intermediate bit sequence comprises: encoding the intermediate bit sequence to generate an encoded bit sequence; and scrambling the encoded bit sequence to generate the output bit sequence (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098).
Regarding claim 3, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 2 on which this claim depends.
Ismail et al. further teach, wherein encoding the intermediate bit sequence comprises using a low-density parity check (LDPC) encoder (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083).
Regarding claim 4, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ismail et al. further teach, wherein processing the intermediate bit sequence comprises: scrambling the intermediate bit sequence to generate a scrambled bit sequence; and encoding the scrambled bit sequence to generate the output bit sequence (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117).
Regarding claim 5, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ismail et al. further teach, wherein the non-volatile memory is a triple-level cell (TLC) and the page type is a most significant bit (MSB) page type, a center significant bit (CSB) page type, or a least significant bit (LSB) page type (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098).
Regarding claim 6, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ismail et al. further teach, wherein a length of the inversion seed is N bits, wherein a length of the flip sequence is 2N bits, and wherein the number of program erase cycles of the non-volatile memory is denoted PEC (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100).
Regarding claim 7, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Ismail et al. further teach, wherein the inversion seed is determined as (PEC % 2N), and wherein % represents a modulo operation (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105).
Regarding claim 8, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 6 on which this claim depends.
Ismail et al. further teach, wherein the inversion seed is determined as ((PEC + PA) % 2N), wherein % represents a modulo operation, and wherein PA is a physical address of the page (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117).
Regarding claim 9, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ismail et al. further teach, wherein the input bit sequence comprises user data and firmware meta data, and wherein the inversion seed is embedded in the firmware meta data (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130).
Regarding claim 10, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ismail et al. further teach, wherein the inversion seed, the flip sequence, and the circular shift flip sequence are identical for pages having a same page type (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083).
Regarding independent claim 11, Ismail et al. teach a system for improving a performance of a non-volatile memory, the system comprising: a firmware configured to generate, based on a number of program erase cycles of the non-volatile memory, an inversion seed for a page type of the non-volatile memory; a hardware controller configured to: generate a circular shift flip sequence based on the inversion seed and a flip sequence (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139, 0151, data sequence in circular shift register, inversion seed in Fig. 4B), and perform a bit-flipping operation on an input bit sequence based on the circular shift flip sequence to generate an intermediate bit sequence; and a memory controller configured to: process the intermediate bit sequence to generate an output bit sequence, and write the output bit sequence to a page in the non-volatile memory, wherein the page is of the page type (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139, 0151, bit flipping in step 4029, write operation in step 403, output sequence read from memory).
Even though Ismail et al. teach program / erase cycle (see paragraph 0003) but silent exclusively about generate, based on a number of program erase cycles of the non-volatile memory.
Lien teaches generating, based on a number of program erase cycles of the non-volatile memory (see Fig. 7-8, paragraph 0046-0058 where data sequence generated from PE input including address).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lien to the teaching of Ismail et al. where computing device 100 of Ismail et al. would be considered as data sequencer 150 taught by Lien and to generate bit sequence in order to yield improved cell distributions and to extend useful life of memory device (see Lien, paragraph 0025, 0067).
Further reason to combine the teachings of Lien and Ismail et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards error correction of flash memory array.
Regarding claim 12, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Ismail et al. further teach, wherein the inversion seed, the flip sequence, and the circular shift flip sequence are identical for pages having a same page type (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095).
Regarding claim 13, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Ismail et al. further teach, wherein a length of the inversion seed is N bits, wherein a length of the flip sequence is 2N bits, and wherein the number of program erase cycles of the non-volatile memory is denoted PEC (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098).
Regarding claim 14, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Ismail et al. further teach, wherein the inversion seed is determined as (PEC % 2N), and wherein % represents a modulo operation (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105).
Regarding claim 15, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 13 on which this claim depends.
Ismail et al. further teach, wherein the inversion seed is determined as ((PEC + PA) % 2N), wherein % represents a modulo operation, and wherein PA is a physical address of the page (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139).
Regarding independent claim 16, Ismail et al. teach a non-transitory computer-readable storage medium having instructions stored thereupon for improving a performance of a non-volatile memory, the instructions, when executed by a processor, cause the processor to perform operations (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139, 0151, unit 150 is processor) comprising: generating, based on a number of program erase cycles of the non-volatile memory, an inversion seed for a page type of the non-volatile memory; generating a circular shift flip sequence based on the inversion seed and a flip sequence (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139, 0151, data sequence in circular shift register, inversion seed in Fig. 4B); performing a bit-flipping operation on an input bit sequence based on the circular shift flip sequence to generate an intermediate bit sequence; processing the intermediate bit sequence to generate an output bit sequence; and writing the output bit sequence to a page in the non-volatile memory, wherein the page is of the page type (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0110-0117, 0130-0139, 0151, bit flipping in step 4029, write operation in step 403, output sequence read from memory).
Even though Ismail et al. teach program / erase cycle (see paragraph 0003) but silent exclusively about generating, based on a number of program erase cycles of the non-volatile memory.
Lien teaches generating, based on a number of program erase cycles of the non-volatile memory (see Fig. 7-8, paragraph 0046-0058 where data sequence generated from PE input including address).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Lien to the teaching of Ismail et al. where computing device 100 of Ismail et al. would be considered as data sequencer 150 taught by Lien and to generate bit sequence in order to yield improved cell distributions and to extend useful life of memory device (see Lien, paragraph 0025, 0067).
Further reason to combine the teachings of Lien and Ismail et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards error correction of flash memory array.
Regarding claim 17, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Ismail et al. further teach, wherein processing the intermediate bit sequence to generate the output bit sequence comprises: encoding the intermediate bit sequence to generate an encoded bit sequence; and scrambling the encoded bit sequence to generate the output bit sequence (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105).
Regarding claim 18, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Ismail et al. further teach, wherein encoding the intermediate bit sequence comprises using a low-density parity check (LDPC) encoder (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098).
Regarding claim 19, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Ismail et al. further teach, wherein processing the intermediate bit sequence to generate the output bit sequence comprises: scrambling the intermediate bit sequence to generate a scrambled bit sequence; and encoding the scrambled bit sequence to generate the output bit sequence (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100).
Regarding claim 20, Ismail et al. and Lien teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Ismail et al. further teach, wherein the non-volatile memory is a triple-level cell (TLC) and the page type is a most significant bit (MSB) page type, a center significant bit (CSB) page type, or a least significant bit (LSB) page type (see Fig. 1-3, 4-11, paragraph 0023-0024, 0029-0031, 0043-0046, 0062-0063, 0066-0067, 0070-0075, 0078-0083, 0095-0098, 0100-0105, 0151).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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