DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3, 4, and 12-16 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 3 recite(s) the language (emphasis added) “wherein the local fast clock signal has a period corresponding to”, where “a period” has already been recited in claim 2 and it is unclear if the recited limitations are different from one another.
Claim(s) 12 recite(s) the language (emphasis added) “a local fast clock domain including a synchronization circuit and a logic circuit”, where “a synchronization circuit” has already been recited in claim 9 and it is unclear if the recited limitations are different from one another.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kulick, US 20180095910 A1.
As to claim 1, Kulick discloses a data receiving circuit (see Fig 1B) comprising:
a forwarded fast clock domain (see Fig 1B Ref 162 and Para [0002]) configured to output data (see Fig 1A Ref 152 and Fig 4 Ref DATA IN) transmitted from a data transmitting circuit (see Fig 1A Ref 110 and 1B Ref 170) in synchronization with a forwarded fast clock signal (see Fig 1B Ref 170 and Paras [0020] and [0031]); and a local clock domain (see Fig 1B Refs 180 and 190 and Para [0032]) in communication with the forwarded fast clock domain and configured to generate a synchronized fetch enable signal (see Fig 4 Ref READ ENABLE) in synchronization with a local fast clock signal (see Fig 1B Ref 162) and output the data transmitted from the forwarded fast clock domain in synchronization with a local slow clock signal (see Fig 1B Ref 164).
As to claim 2, Kulick discloses the data receiving circuit of claim 1, wherein
the local slow clock signal has a period longer than a period of the forwarded fast clock (see Para [0070]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kulick, US 20180095910 A1, in view of Ware, US 20200294557 A1.
As to claim 3, Kulick discloses the data receiving circuit of claim 2, wherein
the local fast clock signal has a period corresponding to the period of the local slow clock signal.
Kulick does not appear to explicitly disclose a period corresponding to 1/N (N is a natural number greater than 2) of the period of the local slow clock signal.
Ware discloses a period corresponding to 1/N (N is a natural number greater than 2) of the period of the local slow clock signal (see Ware Para [0060]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a data receiving circuit, as disclosed by Kulick, may implement particular clock speeds, as disclosed by Ware. The inventions are well known variants of transmission circuits, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Ware’s attempt to correct for timing drift (see Ware Para [0027]).
Claim(s) 3, 5-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kulick, US 20180095910 A1, in view of Mladenov, US 20230186142 A1.
As to claim 3, Kulick discloses the data receiving circuit of claim 2, wherein
the local fast clock signal has a period corresponding to the period of the local slow clock signal.
Kulick does not appear to explicitly disclose a period corresponding to 1/N (N is a natural number greater than 2) of the period of the local slow clock signal.
Ware discloses a period corresponding to 1/N (N is a natural number greater than 2) of the period of the local slow clock signal (see Mladenov Para [0054]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a data receiving circuit, as disclosed by Kulick, may implement particular clock speeds, as disclosed by Mladenov. The inventions are well known variants of transmission circuits, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Mladenov’s attempt to enable high-speed data transfer (see Mladenov Para [0041]).
As to claim 5, Kulick and Mladenov disclose the data receiving circuit of claim 1, wherein
the forwarded fast clock domain includes:
a high speed interface (see Fig 7 Ref 712) configured to perform high speed interfacing on the data transmitted from the data transmitting circuit; and a forwarded data buffer (see Mladenov Fig 4 Ref 402) configured to perform buffering on the data transmitted through the high speed interface, and output the data to the local clock domain in synchronization with the forwarded fast clock signal (see Fig 4 Ref READ ENABLE).
As to claim 6, Kulick and Mladenov disclose the data receiving circuit of claim 5, wherein
the high speed interface is configured to output a data valid signal indicating whether the data transmitted from the data transmitting circuit is valid (see Fig 4 Ref DATA VALID IN and Para [0056]).
As to claim 7, Kulick and Mladenov disclose the data receiving circuit of claim 6, wherein
the forwarded fast clock domain further includes a buffer level comparator (see Fig 4 Ref 410 on the FAST CLOCK DOMAIN side) configured to generate and output a fetch enable signal, based on the data valid signal (see Fig 4 output of 464 and Para [0061]).
As to claim 8, Kulick and Mladenov disclose the data receiving circuit of claim 7, wherein
the buffer level comparator is configured to output the fetch enable signal at a time point (see Para [0044]) when a data timing skew range of the forwarded data buffer for data transmitted from the high speed interface elapses (see Para [0044]).
As to claim 9, Kulick and Mladenov disclose the data receiving circuit of claim 7, wherein
the buffer level comparator is configured to compare the number of valid data derived based on the data valid signal and a target level configuration of the forwarded data buffer (see Fig 4 Ref 432), and generate the fetch enable signal, based on a comparison result (see Fig 4 Ref 452) to transmit the fetch enable signal to a synchronization circuit (see Fig 4 Ref 420).
As to claim 10, Kulick and Mladenov disclose the data receiving circuit of claim 9, wherein
the buffer level comparator is configured to adjust the target level configuration through a training process (see Fig 6 and Paras [0075]-[0078]).
As to claim 11, Kulick and Mladenov disclose the data receiving circuit of claim 9, wherein
the buffer level comparator is configured to: increase the target level configuration when a buffer level of the forwarded data buffer is delayed, and decrease the target level configuration when the buffer level of the forwarded data buffer is shortened (see Paras [0075]-[0078]; Transfers from fast to slow, or slow to fast require the delayed and shortened language.).
As to claim 12, Kulick and Mladenov disclose the data receiving circuit of claim 9, wherein
the local clock domain includes: a local fast clock domain (see Fig 4 the portion of Ref 410 on the SLOW CLOCK DOMAIN side) including a synchronization circuit (see Fig 4 Ref 484) and a logic circuit (see Fig 4 Ref 486); and a local slow clock domain (see Fig 4 Ref 404) including a local data buffer (see Fig 4 Ref 420).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kulick, US 20180095910 A1 and Mladenov, US 20230186142 A1, in view of Margalit, US 11487316 B2.
As to claim 4, Kulick and Mladenov disclose the data receiving circuit of claim 3, wherein
the local fast clock signal has a same period as the forwarded fast clock signal.
Kulick does not appear to explicitly disclose a different phase from the forwarded fast clock signal.
Margalit discloses a different phase from the forwarded fast clock signal (see Margalit Col 4, Lines 17-33 and Fig 5).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a data receiving circuit, as disclosed by Kulick and Mladenov, may implement particular clock speeds, as disclosed by Margalit. The inventions are well known variants of transmission circuits, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Margalit’s attempt to enable correct propagation delays (see Margalit Cols 2-3, Lines 57-9).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chui, US 7958285 B1 discloses a forwarded fast clock domain.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 03/02/2026