DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on August 17, 2026, is acknowledged. The traversal is on the ground(s) that the search of the device would substantially encompass the elements of the method. This is not found persuasive because the device can be made by another and materially different process than that seen in the method described in claims 18-20, and as such, a burden of search would still be present.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 8-12, 15, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by We et al (USPGPUB 20160329284, hereinafter “We”).
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Regarding Claim 1, We teaches (Fig. 1B) a multi-die device comprising: a first IC die (152) and a second IC die (154) disposed at a same tier (first IC die 152 and second IC die 154 can be seen disposed at a same tier); a first interconnecting interface (IC1) disposed on the first IC die (152); a second interconnecting interface (IC2) disposed on the second IC die (154), the first interconnecting interface (IC1) and the second interconnecting interface (IC2) being separated by a molding material (molding material 147 is seen separating dies 152, 154); a first conductive pillar (P1) coupled with the first IC die (152); a second conductive pillar (P2) coupled with the second IC die (154); and an interconnecting die (116) disposed between (interconnecting die 116 is seen disposed between first conductive pillar P1 and second conductive pillar P2) the first conductive pillar (P1) and the second conductive pillar (P2) and configured to couple with (interconnecting die 116 is seen coupled directly with both he first IC die 152 and second IC die 154) the first IC die (152) and the second IC die (154).
Regarding Claim 2, We teaches the multi-die device of claim 1, wherein the first interconnecting interface (IC1) couples the first IC die (152) with the first conductive pillar (P1), the second interconnecting interface (IC2) couples the second IC die (154) with the second conductive pillar (P2).
Regarding Claim 4, We teaches the multi-die device of claim 2, wherein the first conductive pillar (P1) and the second conductive pillar (P2) are configured as a testing structure for testing the first IC die and the second IC die, respectively (As seen in MPEP 2114(II), “A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.”; a testing apparatus would just constitute the pillars being electrically coupled to an external source, as seen in We Fig. 1B).
Regarding Claim 5, We teaches (Fig. 1B) the multi-die device of claim 2, further comprising: a third interconnecting interface (IC3) disposed on surfaces of the first conductive pillar (P1), the second conductive pillar (P2), and the interconnecting die (116), the interconnecting die (116) being disposed between the first interconnecting interface (IC1) and the third interconnecting interface (IC3).
Regarding Claim 8, We teaches the multi-die device of claim 1, further comprising a molding material (147) filing empty spaces among (molding material 147 is seen filling empty spaces among the first IC die 152, second IC die 154, and interconnecting die 116) the first IC die (152), the second IC die (154), and the interconnecting die (116).
Regarding Claim 9, We teaches the multi-die device of claim 1, wherein the first conductive pillar (P1) and the second conductive pillar (P2) have substantially a same height (first conductive pillar P1 and second conductive pillar P2 are seen having substantially the same height).
Regarding Claim 10, We teaches the multi-die device of claim 9, wherein the first conductive pillar (P1) and the interconnecting die (116) have substantially the same height (first conductive pillar P1 and interconnecting die 116 are seen having substantially the same height associated with them, as can be seen in Fig. 1B of We, wherein the first conductive pillar P1 and the interconnecting die 116 have upper surfaces which are at substantially the same level).
Regarding Claim 11, We teaches the multi-die device of claim 9, wherein the first conductive pillar (P1) and the second conductive pillar (P2) are configured to test functionalities of the first IC die (152) and the second IC die (154), respectively (As seen in MPEP 2114(II), “A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.”; a testing configuration of the pillars would just constitute the pillars being electrically coupled to an external source as well as the dies 152, 154, respectively, as seen in We Fig. 1B)..
Regarding Claim 12, We teaches an integrated chip package assembly comprising: a multi-die device; a package substrate (158) coupled with the multi-die device; and wherein the multi-die device comprises: a first IC die (152) and a second IC die (154) disposed at a same tier (first IC die 152 and second IC die 154 are seen disposed at the same tier); a first conductive pillar (P1) coupled with the first IC die (P2); a second conductive pillar (P2) coupled with the second IC die (154); and an interconnecting die (116) disposed between the first conductive pillar (P1) and the second conductive pillar (P2) and configured to couple with the first IC die (152) and the second IC die (154); wherein the multi-die device further comprises a first interconnecting interface (IC1) disposed on the first IC die (152) and a second interconnecting interface (IC2) disposed on the second IC die (154); and wherein the first interconnecting interface (IC1) couples the first IC die (152) with the first conductive pillar (P1), the second interconnecting interface (IC2) couples the second IC die (154) with the second conductive pillar (P2), and the first interconnecting interface (IC1) and the second interconnecting interface (IC2) are separated by a molding material (147).
Regarding Claim 15, We teaches the integrated chip package assembly of claim 14, further comprising: a third interconnecting interface (IC3) disposed on surfaces of the first conductive pillar (P1), the second conductive pillar (P2), and the interconnecting die (116), the interconnecting die (116) being disposed between the first interconnecting interface (IC1) and the third interconnecting interface (IC3).
Regarding Claim 17, We teaches (Fig. 1B) the integrated chip package assembly of claim 12, wherein the first conductive pillar (P1) and the second conductive pillar (P2) have substantially a same height (First and second pillars P1 and P2 are seen having a same height, substantially as they reach the same tier at a top surface thereof), the first conductive pillar (P1) and the interconnecting die (116) have substantially the same height (First pillar P1 and the interconnecting die 116 are seen having a same height, substantially as they reach the same tier at a top surface thereof), and the first conductive pillar (P1) and the second conductive pillar (P2) are configured to test functionalities of the first IC die and the second IC die, respectively (As seen in MPEP 2114(II), “A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.”; a testing apparatus would just constitute the pillars being electrically coupled to an external source, as seen in We Fig. 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over We as applied to claim 2 above, and further in view of Kim (USPGPUB 20230420415)
Regarding Claim 3, We teaches the multi-die device of claim 2, wherein the first interconnecting interface (IC1) couples the first IC die (152) with the interconnecting die (116); and wherein the second interconnecting interface (IC2) couples the second IC die (152) with the interconnecting die (116).
We is silent with regards to interconnecting interfaces formed by a single polymer layer.
Kim teaches (Fig. 7A) interconnecting interfaces formed by a single polymer layer ([0058], “The bonding material layer 12 may include a polymer material having adhesive properties”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the polymer material of Kim into the device of We in order to arrive at the expected result of creating a device which is more structurally stable (See [0058] of Kim) with reasonable expectation of success.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over We as applied to claim 5 above, and further in view of Mahajan et al (USPGPUB 20200286814, hereinafter “Mahajan”).
Regarding Claim 6, We teaches the multi-die device of claim 5, wherein the third interconnecting interface (IC3) comprises a third conductive pillar (P3)
We is silent with regards to coupling with a through silicon via of the interconnecting die.
Mahajan teaches (Fig. 1D) coupling with a through silicon via (127) of the interconnecting die (115a).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the structure of Mahajan into the device of We in order to arrive at the expected result of incorporate a via structure for the known benefit of more signal pathways in the device with reasonable expectation of success.
Regarding Claim 7, We in view of Mahajan teaches the multi-die device of claim 6, wherein the third interconnecting interface (We IC3) comprises a fourth pillar (We P4) coupling with the first conductive pillar (We P1).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over We as applied to claim 12 above, and further in view of Lau et al (USPGPUB 20100213600, hereinafter “Lau”).
Regarding Claim 13, We teaches the integrated chip package assembly of claim 12, but is silent with regards to a stiffener ring surrounding the multi-die device.
Lau teaches (Fig. 1) a stiffener ring surrounding the multi-die device (106; [0044], “ring stiffener 106 is disposed and attached between the substrate 108 and the heat sink 102”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the stiffener of Lau into the device of We in order to arrive at the expected result of creating a more robust device with additional structural support (see [0044] of Lau) with reasonable expectation of success.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over We as applied to claim 12 above, and further in view of Kim.
Regarding Claim 14, We teaches the integrated chip package assembly of claim 12, wherein the first interconnecting interface (IC1) couples the first IC die (152) with the interconnecting die (116); and wherein the second interconnecting interface couples the second IC die with the interconnecting die.
We is silent with regards to an assembly wherein the first interconnecting interface is formed by a single polymer layer and the second interconnecting interface is formed by a single polymer layer.
Kim teaches (Fig. 7A) interconnecting interfaces formed by a single polymer layer ([0058], “The bonding material layer 12 may include a polymer material having adhesive properties”).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the polymer material of Kim into the device of We in order to arrive at the expected result of creating a device which is more structurally stable (See [0058] of Kim) with reasonable expectation of success.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over We as applied to claim 15 above, and further in view of Mahajan.
Regarding Claim 16, We teaches the integrated chip package assembly of claim 15, wherein the third interconnecting interface comprises (IC3) a third pillar (P3) and a fourth pillar (P4) coupling with the first conductive pillar (P1).
We is silent with regards to a device wherein there is coupling with a through silicon via of the interconnecting die.
Mahajan teaches (Fig. 1D) coupling with a through silicon via (127) of the interconnecting die (115a).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the structure of Mahajan into the device of We in order to arrive at the expected result of incorporate a via structure for the known benefit of more signal pathways in the device with reasonable expectation of success.
Conclusion
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/V.J.L./Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
