DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “semiconductor channel material nanosheets increases with a decrease in width of the recessed inner dielectric spacer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al. (U.S. 2025/0089325 A1, hereinafter refer to Hsu).
Regarding Claim 1: Hsu discloses a semiconductor device (see Hsu, Fig.21B as shown below and ¶ [0009]) comprising:
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a p-type field effect transistor (50P) comprising a vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88), a gate structure (120) wrapped around a portion of each semiconductor channel material nanosheet (56B/88) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88), and a strained source/drain region (106) located on each side of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88) (see Hsu, Fig.21B as shown above and ¶ [0043]); and
a recessed inner dielectric spacer (104) located beneath each semiconductor channel material nanosheet (56B/88) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88), wherein the recessed inner dielectric spacer (104) has an outermost sidewall that is located between a width of each semiconductor channel material nanosheet (56B/88) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88) (see Hsu, Fig.21B as shown above).
Regarding Claim 2: Hsu discloses a semiconductor device as set forth in claim 1 as above. Hsu further teaches wherein the strained source/drain region (106) is in compression in a longitudinal direction of current flow (see Hsu, Fig.21B as shown above and ¶ [0043]).
Regarding Claim 3: Hsu discloses a semiconductor device as set forth in claim 1 as above. Hsu further teaches wherein the strained source/drain region (106) is present in in an underhanging region beneath each semiconductor channel material nanosheet (56B/88) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88) and is in direct physical contact with the outermost sidewall of the recessed inner dielectric spacer (104) (see Hsu, Fig.21B as shown above).
Regarding Claim 4: Hsu discloses a semiconductor device as set forth in claim 1 as above. Hsu further teaches wherein each semiconductor channel material nanosheet (56B/88) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88) is composed of silicon, and the strained source/drain region (106) is composed of SiGe (see Hsu, Fig.21B as shown above, ¶ [0019], and ¶ [0043]).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7-11 and 14-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeong et al. (U.S. 2022/0140151 A1, hereinafter refer to Yeong).
Regarding Claim 7: Yeong discloses a semiconductor device (see Yeong, Figs.16-17 as shown below and ¶ [0011]) comprising:
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a p-type field effect transistor comprising a vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54), a gate structure (123) wrapped around a portion of each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54), and a strained source/drain region (112) located on each side of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (see Yeong, Figs.16-17 as shown above and ¶ [0040]- ¶ [0041]);
a recessed inner dielectric spacer (131 and 133) located beneath each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54), wherein the recessed inner dielectric spacer (131/133) has an outermost sidewall that is located between a width of each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (see Yeong, Figs.16-17 as shown above and ¶ [0051]- ¶ [0052]); and
a semiconductor spacer (56) separating the strained source/drain region (112) from each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) and from the recessed inner dielectric spacer (131 and 133) (see Yeong, Figs.16-17 as shown above, ¶ [0038], and ¶ [0050]).
Regarding Claim 8: Yeong discloses a semiconductor device as set forth in claim 7 as above. Yeong further teaches wherein the semiconductor spacer (56) is composed of a compositionally same semiconductor material as each semiconductor channel material nanosheet of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (when, x is 1, both the channel material and semiconductor spacer material will be silicon) (see Yeong, Figs.16-17 as shown above, ¶ [0017], and ¶ [0050]).
Regarding Claim 9: Yeong discloses a semiconductor device as set forth in claim 7 as above. Yeong further teaches wherein the semiconductor spacer (56) is in direct physically contact with an end of each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) and in direct physical contact with the outermost sidewall of the recessed inner dielectric spacer (131/133) (see Yeong, Figs.16-17 as shown above).
Regarding Claim 10: Yeong discloses a semiconductor device as set forth in claim 7 as above. Yeong further teaches wherein the strained source/drain region (112) is in compression in a longitudinal direction of current flow (see Yeong, Figs.16-17 as shown above).
Regarding Claim 11: Yeong discloses a semiconductor device as set forth in claim 7 as above. Yeong further teaches wherein each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) is composed of silicon, and the strained source/drain region (112) is composed of SiGe (when, x is 1, both the channel material and semiconductor spacer material will be silicon) (see Yeong, Figs.16-17 as shown above, ¶ [0017], and ¶ [0041]).
Regarding Claim 14: Yeong discloses a semiconductor device (see Yeong, Figs.16-17 as shown above and ¶ [0011]) comprising:
a p-type field effect transistor comprising a vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54), a gate structure (123) wrapped around a portion of each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54), and a strained source/drain region (112 not including the protrusions 112P) located on each side of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (see Yeong, Figs.16-17 as shown above and ¶ [0040]- ¶ [0041]);
a recessed inner dielectric spacer (131 and 133) located beneath each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54), wherein the recessed inner dielectric spacer (131 and 133) has an outermost sidewall that is located between a width of each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (see Yeong, Figs.16-17 as shown above and ¶ [0051]- ¶ [0052]); and
an inner semiconductor spacer (56 and protrusions 112P) located adjacent to the recessed inner dielectric spacer (131 and 133), wherein the inner semiconductor spacer (56 and protrusions 112P) has an outermost sidewall that is vertically aligned to an end of each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56 and protrusions 112P) (see Yeong, Figs.16-17 as shown above).
Note: the configuration of the claimed inner semiconductor spacer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed inner semiconductor spacer was significant.
Regarding Claim 15: Hsu discloses a semiconductor device as set forth in claim 14 as above. Yeong further teaches wherein the inner semiconductor spacer (56 and protrusions 112P) is composed of a compositionally same semiconductor material as each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (see Yeong, Figs.16-17 as shown above, ¶ [0017], and ¶ [0050]).
Regarding Claim 16: Hsu discloses a semiconductor device as set forth in claim 14 as above. Yeong further teaches wherein the inner semiconductor spacer (56 and protrusions 112P) separates the strained source/drain region (112 not including the protrusions 112P) from the recessed inner dielectric spacer (131/133) (see Yeong, Figs.16-17 as shown above).
Regarding Claim 17: Hsu discloses a semiconductor device as set forth in claim 14 as above. Yeong further teaches wherein the strained source/drain region (112 not including the protrusions 112P) is in compression in a longitudinal direction of current flow (see Yeong, Figs.16-17 as shown above).
Regarding Claim 18: Hsu discloses a semiconductor device as set forth in claim 14 as above. Yeong further teaches wherein each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) is composed of silicon, and the strained source/drain region (112 not including the protrusions 112P) is composed of SiGe (when, x is 1, both the channel material and semiconductor spacer material will be silicon) (see Yeong, Figs.16-17 as shown above, ¶ [0017], and ¶ [0041]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (U.S. 2025/0089325 A1, hereinafter refer to Hsu) as applied to claim 1 above, and further in view of Park et al. (U.S. 2024/0429307 A1, hereinafter refer to Park).
Regarding Claim 5: Hsu discloses a semiconductor device as applied to claim 1 above. Hsu further teaches wherein each semiconductor channel material nanosheet (56B/88) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88) has a stress (see Hsu, Fig.21B as shown above and ¶ [0043]).
Hsu is silent upon explicitly disclosing wherein semiconductor channel material nanosheets has a stress from about 1.5 GPa to about 2.0 GPa.
For support see Park, which teaches wherein semiconductor channel material nanosheets has a stress from about 1.5 GPa to about 2.0 GPa (see Park, ¶ [0056]- ¶ [0059]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Hsu and Park to enable the semiconductor channel material nanosheets of Hsu to have the recited ranges of stress as taught by Park in order to improve hole mobility.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (U.S. 2025/0089325 A1, hereinafter refer to Hsu) and Park et al. (U.S. 2024/0429307 A1, hereinafter refer to Park) as applied to claim 5 above, and further in view of Wang (U.S. 2020/0035676 A1, hereinafter refer to Wang).
Regarding Claim 6: Hsu as modified teaches a semiconductor device as set forth in claim 5 as above. The combination of Hsu and Park further teaches wherein the stress on each semiconductor channel material nanosheet (56B/88) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (56B/88) (see Hsu, Fig.21B as shown above).
The combination of Hsu and Park is silent upon explicitly disclosing wherein semiconductor channel material nanosheets increases with a decrease in width of the recessed inner dielectric spacer.
For support see Wang, which teaches wherein semiconductor channel material nanosheets (630) increases with a decrease in width of the recessed inner dielectric spacer (260) (see Wang, Fig.15 as shown below and ¶ [0005]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Hsu, Park, and Wang to enable the semiconductor channel material nanosheets of the combination of Hsu and Park to increases with a decrease in width of the recessed inner dielectric spacer as taught by Wang in order to improve device performance.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (U.S. 2022/0140151 A1, hereinafter refer to Yeong) as applied to claim 11 above, and further in view of Park et al. (U.S. 2024/0429307 A1, hereinafter refer to Park).
Regarding Claim 12: Hsu discloses a semiconductor device as applied to claim 11 above. Yeong further teaches wherein each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) has a stress (see Yeong, Figs.16-17 as shown above and ¶ [0040]- ¶ [0041]).
Yeong is silent upon explicitly disclosing wherein semiconductor channel material nanosheets has a stress from about 1.5 GPa to about 2.0 GPa.
For support see Park, which teaches wherein semiconductor channel material nanosheets has a stress from about 1.5 GPa to about 2.0 GPa (see Park, ¶ [0056]- ¶ [0059]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yeong and Park to enable the semiconductor channel material nanosheets of Yeong to have the recited ranges of stress as taught by Park in order to improve hole mobility.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (U.S. 2022/0140151 A1, hereinafter refer to Yeong) and Park et al. (U.S. 2024/0429307 A1, hereinafter refer to Park) as applied to claim 12 above, and further in view of Wang (U.S. 2020/0035676 A1, hereinafter refer to Wang).
Regarding Claim 13: Hsu discloses a semiconductor device as applied to claim 12 above. The combination of Yeong and Park further teaches wherein the stress on each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (see Yeong, Figs.16-17 as shown above).
The combination of Yeong and Park is silent upon explicitly disclosing wherein semiconductor channel material nanosheets increases with a decrease in width of the recessed inner dielectric spacer.
For support see Wang, which teaches wherein semiconductor channel material nanosheets (630) increases with a decrease in width of the recessed inner dielectric spacer (260) (see Wang, Fig.15 as shown above and ¶ [0005]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yeong, Park, and Wang to enable the semiconductor channel material nanosheets of the combination of Yeong and Park to increases with a decrease in width of the recessed inner dielectric spacer as taught by Wang in order to improve device performance.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (U.S. 2022/0140151 A1, hereinafter refer to Yeong) as applied to claim 14 above, and further in view of Park et al. (U.S. 2024/0429307 A1, hereinafter refer to Park).
Regarding Claim 19: Hsu discloses a semiconductor device as applied to claim 14 above. Yeong further teaches wherein each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) has a stress (see Yeong, Figs.16-17 as shown above and ¶ [0040]- ¶ [0041]).
Yeong is silent upon explicitly disclosing wherein semiconductor channel material nanosheets has a stress from about 1.5 GPa to about 2.0 GPa.
For support see Park, which teaches wherein semiconductor channel material nanosheets has a stress from about 1.5 GPa to about 2.0 GPa (see Park, ¶ [0056]- ¶ [0059]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yeong and Park to enable the semiconductor channel material nanosheets of Yeong to have the recited ranges of stress as taught by Park in order to improve hole mobility.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (U.S. 2022/0140151 A1, hereinafter refer to Yeong) and Park et al. (U.S. 2024/0429307 A1, hereinafter refer to Park) as applied to claim 19 above, and further in view of Wang (U.S. 2020/0035676 A1, hereinafter refer to Wang).
Regarding Claim 20: Hsu discloses a semiconductor device as applied to claim 19 above. The combination of Yeong and Park further teaches wherein the stress on each semiconductor channel material nanosheet (54) of the vertical stack of stressed and spaced apart semiconductor channel material nanosheets (54) (see Yeong, Figs.16-17 as shown above).
The combination of Yeong and Park is silent upon explicitly disclosing wherein semiconductor channel material nanosheets increases with a decrease in width of the recessed inner dielectric spacer.
For support see Wang, which teaches wherein semiconductor channel material nanosheets (630) increases with a decrease in width of the recessed inner dielectric spacer (260) (see Wang, Fig.15 as shown above and ¶ [0005]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Yeong, Park, and Wang to enable the semiconductor channel material nanosheets of the combination of Yeong and Park to increases with a decrease in width of the recessed inner dielectric spacer as taught by Wang in order to improve device performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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