Prosecution Insights
Last updated: October 22, 2026
Application No. 18/773,923

SEMICONDUCTOR DEVICE AND RELATED METHODS

Non-Final OA §102§103
Filed
Jul 16, 2024
Priority
Jan 30, 2024 — provisional 63/626,626
Examiner
BOATMAN, CASEY PAUL
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
1y 3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
71 granted / 84 resolved
+16.5% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
14 currently pending
Career history
110
Total Applications
across all art units

Statute-Specific Performance

§103
49.2%
+9.2% vs TC avg
§102
29.7%
-10.3% vs TC avg
§112
20.7%
-19.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 84 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation Regarding Claims 2-4, the instant application describes the isolation structure including a first refill layer, a second refill layer, and a third refill layer. Paragraph [0054] further describes alternative embodiments wherein the second refill layer may be “the same as the first refill layer” (as drawn to CPODE structure 913 and Claim 4) or the first refill layer may be different than the second refill layer (as drawn to the CPODE structure of 713 and Claim 3). As such, an embodiment wherein the second refill layer may be “the same as the first refill layer” is interpreted to mean that the first refill layer may be a first portion of a refill layer and the second refill layer may be a second portion of the refill layer as shown in Fig. 9A. Claim Rejections - 35 USC § 102 (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 5-10 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko (US 20220367286 A1). Regarding Claim 1, Ko teaches a method (see Figs. 8B-16), comprising: providing a partially-fabricated semiconductor device (see Fig. 8B) including a dummy gate structure (34) disposed over a semiconductor layer stack (24, corresponding to a channel region between S/D regions 42); removing the dummy gate structure (shown Fig. 9) and at least a portion of each semiconductor layer of the semiconductor layer stack to form a trench (56); forming one or more refill layers in a bottom portion of the trench (58 and 60, shown Fig. 11); and forming one or more refill layers (70 and 73 shown Fig. 16) in a top portion of the trench over the bottom portion of the trench, wherein the one or more refill layers in the top and bottom portions of the trench respectively define top and bottom portions of an isolation structure (a top portion corresponding to layers 73 and 70), and wherein at least one refill layer of respective ones of the top and bottom portions of the isolation structure have a different material composition (see [0032] describing layer 58 being SiO2, [0033] describing layer 60 being SiN, and [0036] which cites that layer 70 may be the same as layer 60 or different, with an exemplary material being Si3N4). Regarding Claim 2, Ko teaches the method of claim 1, wherein the bottom portion of the isolation structure includes a first refill layer (60), and wherein the top portion of the isolation structure includes a second refill layer (73, see [0038] and a third refill layer (70) over the second refill layer (shown Fig. 16). Regarding Claim 3, Ko teaches the method of claim 2, wherein the first, second, and third refill layers are different from each other (see [0033], [0036] and [0038]). Regarding Claim 5, Ko teaches the method of claim 1, wherein the bottom portion of the isolation structure includes an SiO-like material (58, see [0033]), and wherein the top portion of the isolation structure includes an SiN-like material (see [0036]). Regarding Claim 6, Ko teaches the method of claim 1, wherein the bottom portion of the isolation structure includes a fixed-charge free material (58 being SiO2, see also [0031]). Regarding Claim 7, Ko teaches the method of claim 1, wherein the isolation structure includes an air gap, a seam, or a combination thereof (62 and 72, shown Fig. 16). Regarding Claim 8, Ko teaches the method of claim 1, wherein the top portion of the isolation structure extends into an underlying substrate by a first depth (bottom of recess 66, shown Fig. 11, see also [0035]), wherein a top surface (22A, shown Fig. 16, see also [0035]) of an adjacent shallow trench isolation (STI) feature (22) extends into the underlying substrate by a second depth (see Fig. 16), and wherein a bottom surface (22B) of the adjacent STI feature extends into the underlying substrate by a third depth (see Fig. 16 and [0035]). Regarding Claim 9, Ko teaches the method of claim 8, wherein the first depth is greater than the second depth, and wherein the first depth is less than the third depth (see [0035] which describes the first depth being between STI surfaces 22A and 22B). Regarding Claim 10, Ko teaches the method of claim 8, wherein a total depth of the isolation structure is greater than the third depth (shown Fig. 16). Regarding Claim 18, Ko teaches a semiconductor device (shown Fig. 16), comprising: an active region (24) including a transistor (including gates 80, channel regions corresponding to 24, and S/D regions 42); and an isolation structure (74) disposed in an isolation region defined at a boundary of the active region (shown Fig. 16); wherein the isolation structure comprises: a bottom portion (58 and 60) including a first refill layer; and a top portion (70) disposed over the bottom portion, the top portion including one or more refill layers; wherein the first refill layer is composed of a different material (SiO2, see [0031]) than at least one of the one or more refill layers (Si3N4, see [0036]). Regarding Claim 19, Ko teaches the semiconductor device of claim 18, wherein the isolation structure includes an air gap, a seam, or a combination thereof (62 and 72, shown Fig. 16). Regarding Claim 20, Ko teaches the semiconductor device of claim 18, further including a shallow trench isolation (STI) feature (22) adjacent to the active region (shown Fig. 16), wherein the top portion of the isolation structure extends into an underlying substrate by a first depth (see Fig. 11, defined by bottom of recess 66, see also [0035]), wherein a top surface (22A) of the STI feature extends into the underlying substrate by a second depth (shown Fig. 16), wherein a bottom surface (22B) of the STI feature extends into the underlying substrate by a third depth (shown Fig. 16), and wherein the first depth is greater than the second depth and less than the third depth (see [0035] describing the first depth being between the second depth and third depth). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 4 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko (US 20220367286 A1) or, in the alternative, under 35 U.S.C 103 as being obvious over Ko (US 20220367286 A1). Regarding Claim 4, Ko teaches the method of claim 2. As alternatively mapped to claim 2, Ko teaches the method of claim 1 wherein the bottom portion of the isolation structure includes a first refill layer (58, thin portion), and wherein the top portion of the isolation structure includes a second refill layer (58, thick portion) and a third refill layer (70) over the second refill layer. As interpreted above, Ko further teaches that the first refill layer is the same as the second refill layer (see also paragraph [0054] and Fig. 9A of the instant application, mapping portions 802T-1 and 602B-1 as a first and second refill layer and being “the same”). In the event that the above interpretation of Ko is not believed to be sufficient evidence to anticipate Claim 4, it would further be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to define a bottom portion of the silicon dioxide layer in the bottom of the trench of Ko to be a first refill layer and a top portion of the silicon dioxide layer in the top of the trench to be defined as a second refill layer, wherein the first refill layer is the same as the second refill layer (as defined in Fig. 9A of the instant application). Allowable Subject Matter Claims 11-17 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 11, the most relevant prior art of record being Ko (US 20220367286 A1) teaches a method, comprising: forming a trench (56, shown Fig. 9) through a dummy device structure (30, a dummy gate stack) in an isolation region of a substrate (shown Fig. 16, corresponding to isolation structure 74); forming, in a bottom portion of the trench, a first refill layer (58); conformally depositing a second refill layer (60) within the bottom portion of the trench over the exposed first refill layer and within a top portion of the trench (shown Fig. 10); and forming a third refill layer (70) within the top portion of the trench including over the second refill layer, wherein the first, second, and third refill layers in the top and bottom portions of the trench provide an isolation structure (74) in the isolation region, and wherein the first refill layer is composed of a different material than at least one of the second and third refill layers (layer 58 being silicon oxide and layers 60 and 70 being silicon nitride). The prior art does not explicitly teach or suggest in any combination a step of forming a sacrificial layer over the first refill layer, removing the sacrificial layer to expose the first refill layer, and forming the third refill layer to further be within the bottom portion of the trench over the second refill layer as described in method 1600 (see also Fig. 16) of the instant application, which allows refill material layers to be at least partially deposited within the bottom portion of the trench as described in [0039]. As such, claim 11 is deemed patentable over the prior art. Claims 12-17 are further deemed patentable as they require all limitations of claim 11. As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Wu (US 20230065498 A1) teaches a CPODE process creating an isolation structure (510, shown Fig. 5C) wherein a bottom portion of a trench is filled with a first refill (504) made of silicon oxide, an upper portion of the trench is filled with a second refill (506) which may be made of SiN, DSiN, or a multilayer DSiN+SiN+DSiN structure (see also [0042]). Jun (US 20180261596 A1) teaches a fin isolation structure (120A) comprising multiple insulating layers (122, 124, 126 and 128) stacked laterally adjacent to each other and including silicon oxide and silicon nitride layers. Lin (US 20190229010 A1) teaches a fin isolation structure (P1 and P2) comprising a bottom portion (P2) and upper portion (P1) comprising a multilayer insulating material (IS2, see also [0033]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.P.B./Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 16, 2024
Application Filed
Sep 26, 2024
Response after Non-Final Action
Oct 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+9.7%)
3y 7m (~1y 3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 84 resolved cases by this examiner. Grant probability derived from career allowance rate.

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