Prosecution Insights
Last updated: April 19, 2026
Application No. 18/773,949

MAGNETIC MEMORY DEVICE

Non-Final OA §102§103
Filed
Jul 16, 2024
Examiner
TRAN, ANTHAN
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
629 granted / 760 resolved
+14.8% vs TC avg
Minimal +2% lift
Without
With
+2.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
25 currently pending
Career history
785
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
33.6%
-6.4% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 760 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I in the reply filed on 02/20/2026 is acknowledged. Information Disclosure Statement IDS filed on 07/16/2024 is fully considered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibata et al. (US Pub. 2022/0109102). Regarding claim 1, Fig. 3 of Shibata discloses a magnetic memory device comprising: a lower magnetic track layer [middle layer 11] extending in a first direction [horizontal direction] and including a plurality of first magnetic domains [A1, A3, and A2]; a spacer layer [12] on the lower magnetic track layer [middle layer 11] and extending in the first direction [horizontal direction]; an upper magnetic track layer [upper layer 11] on the spacer layer [12] and extending in the first direction [horizontal], the upper magnetic track layer including a plurality of second magnetic domains [A1, A3, and A2]; and a plurality of read units [combination of 50 and 71, and combination of 72 and 60 are conductors that connected bit lines to the storage element 100 to transfer reading current. Therefore, 71 and 72 can be considered read units] on the upper magnetic track layer [upper layer 11] and arranged apart from one another in the first direction [71 and 72 are apart from each other in horizontal direction], wherein the plurality of first magnetic domains [A1, A3, and A2 for middle layer 11] and the plurality of second magnetic domains [A1, A3, and A2 for upper layer 11] have magnetization directions parallel to each other [clearly shows in the arrows for each domain A1, A3, and A2] at positions overlapping each other in a second direction perpendicular to the first direction [as discloses in paragraph 0054 and as shows in Fig. 3, the domains for each layer 11 is overlapping each other]. Regarding claim 2, Fig. 3 of Shibata discloses wherein a magnetization direction of the upper magnetic track layer [upper layer 11] is equal to a magnetization direction of the lower magnetic track layer [middle layer 11] based on a leakage magnetic field of the lower magnetic track layer, such that the magnetization direction of the upper magnetic track layer and the magnetization direction of the lower magnetic track layer are formed in parallel to each other [as shows in Fig. 3, the magnetization direction for each domain for layer 11 are parallel and equal, base on the leakage magnetic field of layer 20 that causes the magnetization of lower layer and upper layer 11]. Regarding claim 3, Fig. 3 of Shibata discloses wherein each of the plurality of read units is a pinned layer of a magnetic tunnel junction structure [fixed layer 50 and 60, paragraph 0054], wherein the upper magnetic track layer is a free layer [upper layer 11 is a free layer because its magnetization is not fixed] of the magnetic tunnel junction structure, and wherein each of the plurality of read units is configured to read a magnetization direction of the upper magnetic track layer [combination of 50&71 and 60&72 are part of read circuit]. Regarding claim 10, Fig. 3 of Shibata discloses a conductive layer [E] under the lower magnetic track layer [middle layer 11] and extending in the first direction [horizontal], wherein a length of the conductive layer [E], a length of the lower magnetic track layer [middle layer 11], a length of the spacer layer [12], and a length of the upper magnetic track layer [upper layer 11] are equal to one another in the first direction [clearly shows in Fig. 3]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. (US Pub. 2022/0109102) in view of Heo et al. (US Pub. 2016/0020280). Regarding claim 9, paragraph 0066 of Shibata discloses wherein a thickness of the spacer layer 12 is about 1 nm, but does not specifically disclose the spacer layer comprises hexagonal boron nitride (h-BN). However, Fig. 1 of Heo discloses a spacer layer N10 and N20 comprises hexagonal boron nitride (paragraph 0100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Heo’s spacer layer comprises h-BN to the teachings of Shibata’s spacer layer such that Shibata spacer layer operate in a manner according to Heo’s teachings for the purpose of function as a hole or electron transporter [paragraph 0100]. Allowable Subject Matter Claims 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 4-8, the prior art does not teach or suggest either alone or in combination wherein the lower magnetic track layer comprises: 2N+1 (where N is a natural number) number of first magnetic layers; and 2N number of coupling layers between the 2N+1 number of first magnetic layers. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHAN TRAN/Primary Examiner, Art Unit 2825
Read full office action

Prosecution Timeline

Jul 16, 2024
Application Filed
Mar 06, 2026
Non-Final Rejection — §102, §103
Apr 15, 2026
Interview Requested

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12586631
MEMORY DEVICE HAVING LOAD OFFSET MISMATCH COMPENSATION
2y 5m to grant Granted Mar 24, 2026
Patent 12567463
THREE-STATE PROGRAMMING OF MEMORY CELLS
2y 5m to grant Granted Mar 03, 2026
Patent 12562225
HYBRID MEMORY FOR NEUROMORPHIC APPLICATIONS
2y 5m to grant Granted Feb 24, 2026
Patent 12548605
INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
2y 5m to grant Granted Feb 10, 2026
Patent 12548606
MULTI-MODE COMPATIBLE ZQ CALIBRATION CIRCUIT IN MEMORY DEVICE
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.2%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 760 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month