DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (US Pub. 2024/0420772).
Regarding claims 1, 10, and 20, Fig. 19 of Park disclose a system [Fig. 5], comprising: a memory device, comprising: a memory cell array [200, Fig. 8] comprising a plurality of blocks [SB1 to SB3], wherein the plurality of blocks comprises a first block [SB1, Fig. 19], a second block [SB3, Fig. 19], and a third block [SB2, Fig. 19] located between the first and second blocks [SB1, SB3, respectively] in a plane of the memory device; a peripheral circuit [430, Fig. 8] coupled to the memory cell array [200, Fig. 8], and configured to: select the first and second blocks [SB1, SB3 are selected (SEL)] from the plurality of blocks, wherein the third block [SB2 is unselected (UNS)] is unselected while the first and second blocks are being selected [clearly shows in Fig. 19]; and perform a first erase operation on the first and second blocks in a first period of time [as shows in Fig. 20, SB1 and SB3 are selected to erase during the time between T33 and T35]; and a memory controller [450, Fig. 8] coupled to the memory device and configured to control an operation of the memory device [control 450 control reading, programming, and erasing operations of memory device].
Regarding claims 2 and 11, Fig. 22 of Park discloses selecting the third block [SB2] from the memory device; and performing a second erase operation on the third block in a second period of time [between T44 to T45] that is different from the first period of time.
Regarding claims 3 and 13, Fig. 8 of Park discloses wherein the memory device comprises a peripheral circuit [430] coupled to the plurality of blocks [within array 200], and selecting the first block and the second block from the memory device comprises: unselecting, by the peripheral circuit [as shows in Fig. 8, Address Decoder 430 generating wordline signals (WLs) to select memory blocks in Fig. 19], the plurality of blocks [SB1 to SB3 in Fig. 19]; and for each block in the first and second blocks, responsive to receiving a block address [R_ADDR] of the corresponding block, generating, by the peripheral circuit [430], a block-select signal [WL1 to WL12, Fig. 19] having a block-select value to select the corresponding block, wherein the block-select signal is stored in a block address latch [latch 470 in Fig. 14, within controller 450] associated with the corresponding block.
Regarding claims 4 and 14, Fig. 19 of Park discloses wherein unselecting the plurality of blocks comprises: resetting [by generating low signal for WL5 to WL8], by the peripheral circuit [430 in Fig. 8], a plurality of block address latches associated with the plurality of blocks to an unselect state [low state], so that the plurality of blocks are unselected.
Regarding claims 5 and 15, Fig. 8 of Park discloses wherein generating the block-select signal further comprises: responsive to receiving the block address [R_ADDR, since R_ADDR is used to select a block, it can be considered block address] of the corresponding block [SB1 to SB3] and a state of a block labeling latch associated with the corresponding block indicating that the corresponding block is a functioning block, generating the block-select signal [WLs] having the block-select value [high state = selected state].
Regarding claims 6 and 16, Fig. 8 of Park discloses wherein the memory device comprises a peripheral circuit [430] coupled to the plurality of blocks [SB1 to SB3 within array 200], and selecting the first block [SB1] and the second block [SB2] from the memory device comprises: labeling, by the peripheral circuit, the plurality of blocks [SB2] as bad blocks [not ready to erase is equivalent to bad]; relabeling, by the peripheral circuit, the first [SB1] and second [SB3] blocks as functioning blocks [ready to erase]; and selecting, by the peripheral circuit [430], the first and second blocks relabeled as the functioning blocks based on a select-all-block signal [WLs].
Regarding claims 7 and 17, Fig. 8 of Park discloses labeling the plurality of blocks as the bad [bad is a relative term. Not ready to erase can be considered bad] blocks comprises: setting, by the peripheral circuit [430], a plurality of block labeling latches associated with the plurality of blocks to a bad block state [unselected state], so that the plurality of blocks [SB2] are labeled as the bad blocks; and relabeling the first and second blocks [SB1, SB3] as the functioning blocks comprises: for each block in the first and second blocks, setting, by the peripheral circuit, a block labeling latch associated with the corresponding block to a functioning block state [ready and selected state], so that the corresponding block is relabeled as a functioning block [selected block].
Regarding claims 8 and 18, Fig. 8 of Park discloses wherein selecting the first and second blocks [SB1, SB3] relabeled as the functioning blocks based on the select-all-block signal comprises: generating, by the peripheral circuit [430], first block-select signals [WL1 to WL4 and WL9 to WL12] having a block-select value [high] to select the first and second blocks [SB1, SB3], respectively, based on the select-all-block signal [R_ADDR]; and generating, by the peripheral circuit, second block-select signals [WL5 to WL8] having a block-unselect value to unselect remaining blocks in the plurality of blocks [SB2], respectively, based on the select-all-block signal.
Regarding claims 9 and 19, Fig. 19 and Fig. 20 of Park discloses wherein performing the first erase operation on the first and second blocks [SB1, SB3] in the first period of time comprises: applying an erase voltage [VERS] to erase the first and second blocks in the first period of time [between T33 and T37] while the first and second blocks are being selected [SEL]; and applying a verify voltage [vev2] to verify the erasing of the first and second blocks in the first period of time [between T36 and T37].
Regarding claim 12, Fig. 8 of Park discloses wherein the peripheral circuit [430] comprises: a plurality of block select circuits [within circuit 430, circuits that generating plurality word line signals WLs] corresponding to the plurality of blocks [SB1 to SB3, Fig. 19], respectively; and control logic [450] configured to control an operation of the plurality of block select circuits.
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825