DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 07/16/2026 in which claims 1, 10, and 20 are amended has been entered of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub. 2024/0420772) in view of Iwai et al. (US Pub. 2012/0069660).
Regarding claims 1, 10, and 20, Fig. 19 of Park disclose a system [Fig. 5], comprising: a memory device, comprising: a memory cell array [200, Fig. 8] comprising a plurality of blocks [SB1 to SB3], wherein the plurality of blocks comprises a first block [SB1, Fig. 19], a second block [SB3, Fig. 19], and a third block [SB2, Fig. 19] located between the first and second blocks [SB1, SB3, respectively] in a plane of the memory device; wherein the first block [SB1] comprises first memory strings coupled to a first common source line [CSL], the second block [SB3] comprises second memory strings coupled to a second common source line [CSL], and the third block [SB2] comprises third memory strings coupled to a third common source line [CSL], a peripheral circuit [430, Fig. 8] coupled to the memory cell array [200, Fig. 8], and configured to: select the first and second blocks [SB1, SB3 are selected (SEL)] from the plurality of blocks, wherein the third block [SB2 is unselected (UNS)] is unselected while the first and second blocks are being selected [clearly shows in Fig. 19]; and perform a first erase operation on the first and second blocks in a first period of time [as shows in Fig. 20, SB1 and SB3 are selected to erase during the time between T33 and T35]; and a memory controller [450, Fig. 8] coupled to the memory device and configured to control an operation of the memory device [control 450 control reading, programming, and erasing operations of memory device].
Park discloses all claimed invention, but does not specifically disclose wherein the first common source line, the second common source line, and the third common source line are different common source lines. However, Fig. 3 of Iwai discloses a memory device having multiple blocks (BK1, BK2, and BLn), wherein BK2 is between BK1 and Bkn, and each block has its own common source lines, disclose wherein the first common source line [SL1], the second common source line [SL2], and the third common source line [SLn] are different common source lines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Iwai’s memory blocks to the teachings of Park’s memory having multiple blocks such that each memory block in Park has different source line an arrangement according to Iwai’s teachings for the purpose of controlling each block more independently.
Regarding claims 2 and 11, Fig. 22 of Park discloses selecting the third block [SB2] from the memory device; and performing a second erase operation on the third block in a second period of time [between T44 to T45] that is different from the first period of time.
Regarding claims 3 and 13, Fig. 8 of Park discloses wherein the memory device comprises a peripheral circuit [430] coupled to the plurality of blocks [within array 200], and selecting the first block and the second block from the memory device comprises: unselecting, by the peripheral circuit [as shows in Fig. 8, Address Decoder 430 generating wordline signals (WLs) to select memory blocks in Fig. 19], the plurality of blocks [SB1 to SB3 in Fig. 19]; and for each block in the first and second blocks, responsive to receiving a block address [R_ADDR] of the corresponding block, generating, by the peripheral circuit [430], a block-select signal [WL1 to WL12, Fig. 19] having a block-select value to select the corresponding block, wherein the block-select signal is stored in a block address latch [latch 470 in Fig. 14, within controller 450] associated with the corresponding block.
Regarding claims 4 and 14, Fig. 19 of Park discloses wherein unselecting the plurality of blocks comprises: resetting [by generating low signal for WL5 to WL8], by the peripheral circuit [430 in Fig. 8], a plurality of block address latches associated with the plurality of blocks to an unselect state [low state], so that the plurality of blocks are unselected.
Regarding claims 5 and 15, Fig. 8 of Park discloses wherein generating the block-select signal further comprises: responsive to receiving the block address [R_ADDR, since R_ADDR is used to select a block, it can be considered block address] of the corresponding block [SB1 to SB3] and a state of a block labeling latch associated with the corresponding block indicating that the corresponding block is a functioning block, generating the block-select signal [WLs] having the block-select value [high state = selected state].
Regarding claims 6 and 16, Fig. 8 of Park discloses wherein the memory device comprises a peripheral circuit [430] coupled to the plurality of blocks [SB1 to SB3 within array 200], and selecting the first block [SB1] and the second block [SB2] from the memory device comprises: labeling, by the peripheral circuit, the plurality of blocks [SB2] as bad blocks [not ready to erase is equivalent to bad]; relabeling, by the peripheral circuit, the first [SB1] and second [SB3] blocks as functioning blocks [ready to erase]; and selecting, by the peripheral circuit [430], the first and second blocks relabeled as the functioning blocks based on a select-all-block signal [WLs].
Regarding claims 7 and 17, Fig. 8 of Park discloses labeling the plurality of blocks as the bad [bad is a relative term. Not ready to erase can be considered bad] blocks comprises: setting, by the peripheral circuit [430], a plurality of block labeling latches associated with the plurality of blocks to a bad block state [unselected state], so that the plurality of blocks [SB2] are labeled as the bad blocks; and relabeling the first and second blocks [SB1, SB3] as the functioning blocks comprises: for each block in the first and second blocks, setting, by the peripheral circuit, a block labeling latch associated with the corresponding block to a functioning block state [ready and selected state], so that the corresponding block is relabeled as a functioning block [selected block].
Regarding claims 8 and 18, Fig. 8 of Park discloses wherein selecting the first and second blocks [SB1, SB3] relabeled as the functioning blocks based on the select-all-block signal comprises: generating, by the peripheral circuit [430], first block-select signals [WL1 to WL4 and WL9 to WL12] having a block-select value [high] to select the first and second blocks [SB1, SB3], respectively, based on the select-all-block signal [R_ADDR]; and generating, by the peripheral circuit, second block-select signals [WL5 to WL8] having a block-unselect value to unselect remaining blocks in the plurality of blocks [SB2], respectively, based on the select-all-block signal.
Regarding claims 9 and 19, Fig. 19 and Fig. 20 of Park discloses wherein performing the first erase operation on the first and second blocks [SB1, SB3] in the first period of time comprises: applying an erase voltage [VERS] to erase the first and second blocks in the first period of time [between T33 and T37] while the first and second blocks are being selected [SEL]; and applying a verify voltage [vev2] to verify the erasing of the first and second blocks in the first period of time [between T36 and T37].
Regarding claim 12, Fig. 8 of Park discloses wherein the peripheral circuit [430] comprises: a plurality of block select circuits [within circuit 430, circuits that generating plurality word line signals WLs] corresponding to the plurality of blocks [SB1 to SB3, Fig. 19], respectively; and control logic [450] configured to control an operation of the plurality of block select circuits.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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