DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-11, 13-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoon et al. (US Pub. 2012/0008433).
Regarding claim 8, Fig. 8A of Yoon discloses an apparatus comprising:
a latch array [134] comprising a plurality of latches [LAT1 to LAT5] coupled in series, wherein the plurality of latches are arranged in a plurality of portions [each latch can be considered a portion];
a plurality of clock circuits [CLK], each associated with one of the plurality of portions [each clock signal CLK is inputted to each latch] and configured to provide a respective one of a plurality of clock signals [can be the same clock signals CLK splitting into plurality of signals to input to each latch as shows in Fig. 8A] to the associated one of the plurality of portions [LAT1 to LAT5], wherein each of the plurality of clock circuits is configured to toggle the respective one of the plurality of clock signals responsive to a command being in one of the plurality of latches which is part of the associated one of the plurality of portions [the toggling of clock signal for each latch combine with SHIFT signal, shifting the command ODT from LAT1 to LAT5 and output the command ODT_SHIFT] or about to enter the associated one of the plurality of portions.
Regarding claim 9, Fig. 8A of Yoon discloses wherein the plurality of clock circuits are configured to toggle the respective one of the plurality of clock signals [CLK for each latch] responsive to the command being within N latches of the final latch of the previous one of the plurality of portions [command ODT shift from LAT1 to LAT5 corresponding to each clock CLK and SHIFT signals].
Regarding claim 10, Fig. 8A of Yoon discloses wherein the command is a read auto-precharge command and the latch array is part of an tRTP shifter or the command is a write auto-precharge command and the latch array is part of a tWR shifter [as discloses in paragraphs 0004 and 0059 command ODT is a read command to perform read operation].
Regarding claim 11, Fig. 8A of Yoon discloses wherein each of the plurality of latches [LAT1 to LAT5] is configured to provide a respective one of a plurality of busy signals [since applicant does not clarify what a busy signal is, it can be a signal output from each LAT1 to LAT5] at an active level when the command [ODT] is in the respective one of the plurality of latches.
Regarding claim 13, Fig. 8A and Fig. 10 of Yoon disclose wherein selected ones of the plurality of clock circuits [CLK] are additionally configured to begin toggling the respective one of the plurality of clock signals [CLK] responsive to a setting [SHIFT] indicating a latch in the associated one of the plurality of portions and a command signal [when command ODT is input into the latch] indicating the command is about to enter the latch array.
Regarding claim 14, Fig. 7 of Yoon discloses a mode array [134] configured to store the setting [SHIFT_<N>], wherein the setting indicates [SHIFT_<N> corresponding to CODE_LATENCY indicates length of shift] a length of shift of the command in the latch array.
Regarding claim 15, Fig. 8A of Yoon discloses method comprising:
toggling a clock signal [CLK, as shows in Fig. 10] associated with a row of latches [LAT1 to LAT5] of a latch array [134] of a command shifter when a command [ODT] is in the associated row of latches or about to enter the associated row of latches;
passing the command [ODT] along the associated row of latches when the clock signal is toggling [ODT is passing from LAT1 to LAT5]; and
stopping toggling the clock signal when the command leaves the associated row of latches [when ODT output from LAT5 and then device is off or inactive].
Regarding claim 16, Fig. 8A of Yoon discloses toggling the clock signal responsive to a setting [SHIFT] indicating one of the latches of the associated row of latches and a signal indicating the command [ODT] is about to enter the latch array [activates latches when ODT is inputted].
Regarding claim 17, Fig. 8B of Yoon discloses passing an internal clock signal [CLK can be considered internal clock signal] as the toggling clock signal.
Regarding claim 19, Fig. 8A of Yoon discloses skipping one or more latches of the latch array responsive to a setting [if SHIFT latency is longer].
Regarding claim 20, Fig. 8A of Yoon discloses providing a ready pulse signal when the command exits the latch array [SHIFT signal to select and activate a latch can be considered a ready pulse signal].
Allowable Subject Matter
Claims 1-7 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 1-7, the prior art does not teach or suggest either alone or in combination an apparatus comprising: a second row of latches coupled in series, each coupled in common to a second clock signal and configured to pass the command along the second row of latches responsive to the second clock signal toggling, wherein a first latch of the second row of latches is coupled in series with a last latch of the first row of latches; a first clock circuit configured to toggle the first clock signal when the command is in the first row of latches; and a second clock circuit configured to toggle the second clock signal when the command is in the last latch of the first row of latches or one of the latches the second row of latches.
Claim 12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12, the prior art does not teach or suggest either alone or in combination wherein each of the plurality of clock circuits is configured to receive a portion of the plurality of busy signals provided by the associated one of the plurality of portions.
Regarding claim 18, the prior art does not teach or suggest either alone or in combination: activating a clock enable signal responsive to busy signals provided by the latches of the associated row of latches or a busy signal from a final latch of the previous row of latches; and toggling the clock signal responsive to the active clock enable signal.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825