DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wang (US 20230033603) herein referred to as Wang.
As to claim 1, Wang teaches a semiconductor structure, comprising:
a base substrate ([0043] substrate 200);
a channel layer structure ([0043] “As shown in FIG. 4, a plurality of initial channel layers 201 and a plurality of initial sacrificial layers 202 may be formed on the substrate 200”), disposed above the base substrate (), wherein
the channel layer structure (Fig. 4) includes one or more channel layers ([0043] “As shown in FIG. 4, a plurality of initial channel layers 201”) spaced apart from each other;
a gate structure ([0082] “Each gate structure 212”), on the base substrate (200) and crossing the channel layer structure (Fig. 10), wherein
the gate structure ([0082] “Gate structures 212”) surrounds the one or more channel layers (201) along an extension direction of the gate structure (212); and
a gate structure (212) between adjacent channel layers and between the channel layer structure (Fig. 4) and the base substrate (200) is configured as a stacked layer gate ();
a source-drain doped layer ([0079] “As shown in FIG. 16, after the source/drain doped layer 210”), on the base substrate (200) at two sides of the gate structure (212) and in contact with an end of the channel layer structure (Fig. 4); and
inner spacers ([0067] “inner spacers 209”), at a sidewall of the stacked layer gate (Annotated Fig. 17 stacked layer gate) and embedded in the source-drain doped layer (210), wherein
the stacked layer gate (Annotated Fig. 17 stacked layer gate) and the source-drain doped layer (210) are spaced apart by the inner spacers (209).
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As to claim 2, Wang teaches the semiconductor structure according to claim 1, and further discloses wherein:
the sidewall of the stacked layer gate (Annotated Fig. 17 stacked layer gate) is coplanar with a sidewall of a channel layer. (201)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20230033603) in view of Chien-Li Cheng et al. (US 20080268602) herein referred to as Cheng.
As to claim 3, Wang teaches the semiconductor structure according to claim 1, wherein:
along an extension direction of the channel layer structure (Fig. 4), a dimension of the inner spacers (209) embedded in the source-drain doped layer (210)
Wang does not explicitly teach “a dimension of the inner spacers embedded in the source-drain doped layer is from about “1 angstrom to about 50 angstrom”. The choice to design the thickness (or lateral length) of the inner spacers embedded in the source-drain region within a range of 1 Angstrom to 50 Angstroms is a careful optimization to balance parasitic capacitance, drive current, short-channel control, and mechanical stability.
However, Cheng et al. teaches in [0004] “offset spacer may be as small as 100 Angstroms”. A prima facie case of obviousness exists where the claimed (range/dimension) and prior art (range/dimension) do not overlap but are close enough that one skilled in the art would have expected them to have the same properties (see MPEP § 2144.05 and Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985)). Furthermore, the Applicant has not shown that a dimension of 100 Angstroms for the offset spacer is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device. In the absence of any indication of the criticality of the (range/dimension) as disclosed in (current claim), it will be taken that the teaching of (prior art) reads on the instant claim.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to make the inner spacers of the Wang device similar to the range of the spacers in the Cheng device. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art in order to optimize the device reliability/design and connectivity requirements owing to the properties of the material. In re AIler, 105 USPQ 233.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Wang (US 20230033603) in view of Wang et al. (US 20210407856) .
As to claim 4, Wang teaches the semiconductor structure according to claim 1, wherein:
the inner spacers (209) include air spacers, dielectric spacers, and/or a combination thereof.
However, Wang does not explicitly teach “the inner spacers include air spacers, dielectric spacers, and/or a combination thereof.” The inner spacers of the Wang device are fabricated using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) and can include air spacers, dielectric spacers, and/or a combination thereof. In advanced semiconductor architectures like Gate-All-Around (GAA) nanosheet transistors, the inner spacer is a critical isolation layer placed between the metal gate and the source/drain regions. Engineers design inner spacers using air spacers, dielectric spacers, or a combination thereof to balance a fundamental engineering trade-off: maximizing raw processing speed by cutting parasitic capacitance versus maintaining structural integrity and gate control.
Secondary reference, Wang et al. teaches in [0057] “According to some embodiments, inner spacer structure 125 having inner air spacer 130 can prevent formation of epitaxial defect.” It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to ensure the Wang device included inner spacers with air spacers, dielectric spacers, and/or a combination thereof such as is in the Wang et al device so as to use an industrially tested and accepted device.
Allowable Subject Matter
Claims 5 is allowed. The following is an examiner’s statement of reasons for allowance: The primary reference, Wang (US 20230033603) teaches a fabrication method of a semiconductor structure, comprising:
As to claim 5, Wang teaches:
providing a base substrate ([0043] substrate 200)), wherein
a stacked layer structure (Annotated Fig. 17 stacked layer gate) is formed on the base substrate (200) and includes
sacrificial layers and channel layers (Fig. 4) alternately stacked from a bottom to a top along a vertical direction; and
a dummy gate structure (204) is further formed on the base substrate (200) crossing the stacked layer structure (Annotated Fig. 17 stacked layer gate) and covers sidewalls and a top of the stacked layer structure (Annotated Fig. 17 stacked layer gate);
forming a source-drain doped layer ([0079] “As shown in FIG. 16, after the source/drain doped layer 210”), on the base substrate at two sides of the dummy gate structure, wherein
the source-drain doped layer (210) is in contact with an end of the stacked layer structure (Annotated Fig. 17 stacked layer gate);
removing the dummy gate structure (204) to form a gate opening;
the channel layer structure includes the channel layers which are spaced apart from each other (Fig. 4), and
As to claims 5, the prior art, Wang fails to teach the following steps in a different order than the applicant:
removing the sacrificial layers [0045] of the stacked layer structure to form through-grooves and a channel layer structure, wherein
the through-grooves expose the source-drain doped layer (210);
forming inner spacers (209) in the source-drain doped layer (210) exposed by the through-grooves; and
forming a gate structure (212) crossing the channel layer (Fig. 4) structure in the gate opening and the through-grooves, wherein
the gate structure (212) surrounds the channel layers (Fig. 4) along an extension direction of the gate structure; and
the gate structure (212) between adjacent channel layers (Fig. 4) and between the channel layer (Fig. 4) structure and
the base substrate (200) is spaced apart from the source-drain doped layer (210) by the inner spacers (209).
Claims 6-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The prior art taken either singularly or in combination, fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper. The prior art fails to teach a combination of all of the features in the claims.
Claims (6-17) are allowable at least because they depend from allowable claims 5.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
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