Prosecution Insights
Last updated: October 02, 2026
Application No. 18/774,145

DOHERTY AMPLIFICATION CIRCUIT

Non-Final OA §102§103
Filed
Jul 16, 2024
Priority
Feb 24, 2022 — JP 2022-026795 +1 more
Examiner
NGUYEN, KHIEM D
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1928 granted / 2248 resolved
+25.8% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
60 currently pending
Career history
2283
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
28.8%
-11.2% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2248 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which has been placed of record in the file. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/16/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 4 & 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bouisse (US 20200382069 A1). Regarding claim 1: Bouisse discloses in Figs. 5 & 8, a Doherty amplification circuit comprising: a carrier amplifier (Fig. 5, amplifier 132) that is a single-stage or multistage amplifier; and a first peak amplifier that is a multistage amplifier (includes amplifiers 138 & 538), wherein a number of stages of the first peak amplifier is greater than a number of stages of the carrier amplifier. Regarding claim 4: Bouisse discloses wherein one of the number of stages of the carrier amplifier (single, odd) or the number of stages of the first peak amplifier is odd, and wherein another of the number of stages of the carrier amplifier or the number of stages of the first peak amplifier is even (see Fig. 5, even). Regarding claim 7: Bouisse discloses further comprising: a phase shift circuit (850 of Fig. 8) that is connected between an output terminal (node 155 / RF out) of the carrier amplifier (132) and an output terminal of the Doherty amplification circuit, wherein the output terminal of the carrier amplifier is connected to the output terminal of the Doherty amplification circuit with the phase shift circuit interposed between the output terminal of the carrier amplifier (132) and the output terminal of the Doherty amplification circuit, and wherein an output terminal of the first peak amplifier (peak 538) is connected to the output terminal (155 /RF out) of the Doherty amplification circuit without the phase shift circuit interposed between the output terminal of the first peak amplifier and the output terminal of the Doherty amplification circuit. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouisse. Regarding claims 2 & 3. Bouisse discloses the limitations as applied in claim 1 and further discloses a module substrate (see Fig. 9A-C, 10-11); and at least one integrated circuit (see para. 0021, a depicted device or circuit may be integrated within a larger circuit) that is on the module substrate and that comprises amplification transistors of the carrier amplifier and the first peak amplifier, wherein in plan view of the module substrate (see Fig. 9A-C, 10-11) except for a size of a first stage of the first peak amplifier is smaller than a size of a first stage of the carrier amplifier; and/or (Claim 3) amplification transistors of the carrier amplifier and the first peak amplifier, wherein in plan view of the module substrate, a size of a final stage of the first peak amplifier is equal to a size of a final stage of the carrier amplifier. Bouisse discloses, see para. 0064, For example, the power-handling capability of a Doherty amplifier may be determined by the size of transistors in the main amplifier 132 and peaking amplifier 138. Power may be increased in Doherty amplifiers by increasing the number of transistors (gate conductors, drain contacts, and source contacts) along the linear array of transistors in the main amplifier and the peaking amplifier). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to have chosen or selected a size of a first stage of the first peak amplifier is smaller than a size of a first stage of the carrier amplifier; and/or amplification transistors of the carrier amplifier and the first peak amplifier, wherein in plan view of the module substrate, a size of a final stage of the first peak amplifier is equal to a size of a final stage of the carrier amplifier; and/or a second peak amplifier that is a multistage amplifier, wherein a number of stages of the second peak amplifier is greater than the number of stages of the carrier amplifier since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouisse in view of Baroudi et al. (US 20210167735 A1). Regarding claim 8: Bouisse discloses the limitations as applied in claim 1 except for a second peak amplifier that is a multistage amplifier, wherein a number of stages of the second peak amplifier is greater than the number of stages of the carrier amplifier. Baroudi discloses in Fig. 4 a Doherty amplifier comprising a carrier amplifier 402 and peaking amplifier 404 and duplication peaking amplifier 405. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Bouisse to have added a duplication stage (e.g., peaking amplifier 138 and 538). Such a modification would have imparted the advantageous benefit of improving power and efficiency, see paragraph [0005]). Regarding claims 9-12: Bouisse discloses the limitations as applied in claim 1 and further discloses a module substrate (see Fig. 9A-C, 10-11); and at least one integrated circuit that is on the module substrate and that comprises amplification transistors of the carrier amplifier, the first peak amplifier, and the second peak amplifier, wherein in plan view of the module substrate except for a size of a first stage of the first peak amplifier is smaller than a size of a first stage of the carrier amplifier, and a size of a first stage of the second peak amplifier is smaller than the size of the first stage of the carrier amplifier; and/or wherein the number of stages of the second peak amplifier is greater than the number of stages of the first peak amplifier. Bouisse discloses, see para. 0064, For example, the power-handling capability of a Doherty amplifier may be determined by the size of transistors in the main amplifier 132 and peaking amplifier 138. Power may be increased in a Doherty amplifier by increasing the number of transistors (gate conductors, drain contacts, and source contacts) along the linear array of transistors in the main amplifier and the peaking amplifier). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to have chosen or selected a size of a first stage of the first peak amplifier is smaller than a size of a first stage of the carrier amplifier, and a size of a first stage of the second peak amplifier is smaller than the size of the first stage of the carrier amplifier; and/or wherein the number of stages of the second peak amplifier is greater than the number of stages of the first peak amplifier since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouisse in view of Asbeck et al. (US 20220263475 A1, hereinafter Asbeck). Regarding claim 5: Bouisse discloses the limitations as applied in claim 1 except for a transformer as a combiner. Asbeck discloses in Fig. 1 a Doherty amplifier circuit comprising both main amplifier and an auxiliary amplifier being connected to a transformer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Bouisse to have a transformer as taught by Asbeck. Such a modification would have imparted the advantageous benefit of improving high average efficiency, low loss power, see paragraph [00531) as taught by Asbeck to Bouisse reference, thereby suggesting the obviousness of such a modification. Accordingly, the combination further discloses further comprising: a transformer (Fig. 1 of Asbeck, note that transformer having the same arrangement to the applicant transformer 21 as shown in Fig. 1 of the application, thus connection terminals are similarly) comprising an input side coil and an output side coil; and a phase shift circuit (circuit 144 may be used as a phase shift) that is connected between an output terminal of the first peak amplifier and the transformer, wherein a first end of the input side coil is connected to an output terminal of the carrier amplifier, wherein a second end of the input side coil is connected to the output terminal of the first peak amplifier with the phase shift circuit interposed between the second end of the input side coil and the output terminal of the first peak amplifier, wherein a first end of the output side coil is connected to an output terminal of the Doherty amplification circuit, and wherein a second end of the output side coil is connected to ground. Claim(s) 1, 8 & 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Acimovic et al. (US 8653889 B1, hereinafter Acimovic ) in view of Bouisse. Regarding claim 1: Acimovic discloses in Fig. 4 a Doherty amplifier circuit comprising main amplifier branch 410 and peak amplifier branch 420-1 and peak amplifier branch 420-2 except for a first peak amplifier that is a multistage amplifier, wherein a number of stages of the first peak amplifier is greater than a number of stages of the carrier amplifier. Bouisse discloses Doherty amplifier comprising main amplifier and peaking amplifiers 138 and 538. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Acimovic to have peaking amplifiers as taught by Bouisse. Such a modification would have imparted the advantageous benefit of improving the improved Doherty amplifier may operate at higher gain, see abstract as taught by Bouisse to Acimovic reference, thereby suggesting the obviousness of such a modification. Regarding claim 8: The combination (Bouisse and Acimovic) discloses further comprising: a second peak amplifier (Fig. 4 and peaking 420-2) that is a multistage amplifier, wherein a number of stages of the second peak amplifier is greater than the number of stages of the carrier amplifier (410). Regarding claim 15: The combination (Bouisse and Acimovic) discloses the Doherty amplification circuit according to Claim 8, further comprising: a first phase shift circuit (Fig. 4, element 415 or Z01) that is connected between an output terminal of the carrier amplifier (410) and an output terminal of the Doherty amplification circuit (see he load impedance ZL); and a second phase shift circuit (Z02) that is connected between the output terminal of the carrier amplifier and the output terminal of the Doherty amplification circuit, and between the first peak amplifier and the output terminal of the Doherty amplification circuit, wherein the output terminal of the carrier amplifier is connected to the output terminal of the Doherty amplification circuit with the first phase shift circuit and the second phase shift circuit interposed between the output terminal of the carrier amplifier and the output terminal of the Doherty amplification circuit, wherein an output terminal of the first peak amplifier (420-1) is connected to the output terminal of the Doherty amplification circuit without the first phase shift circuit interposed between the output terminal of the first peak amplifier (420-1) and the output terminal of the Doherty amplification circuit, and with the second phase shift circuit interposed between the output terminal of the first peak amplifier and the output terminal of the Doherty amplification circuit, and wherein an output terminal of the second peak amplifier (420-2) is connected to the output terminal of the Doherty amplification circuit without the first phase shift circuit and the second phase shift circuit interposed between the output terminal of the second peak amplifier and the output terminal of the Doherty amplification circuit. Allowable Subject Matter Claim(s) 6 & 13-14 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 6 is allowable since the prior art does not disclose about further comprising: a first transformer comprising a first input side coil and a first output side coil; and a second transformer comprising a second input side coil and a second output side coil, wherein a first end of the first input side coil is connected to an output terminal of the carrier amplifier, wherein a second end of the first input side coil is connected to ground, wherein a first end of the first output side coil is connected to an output terminal of the Doherty amplification circuit, wherein a second end of the first output side coil is connected to the second output side coil, wherein a first end of the second input side coil is connected to an output terminal of the first peak amplifier, wherein a second end of the second input side coil is connected to ground, wherein a first end of the second output side coil is connected to the second end of the first output side coil, and wherein a second end of the second output side coil is connected to ground. Claim 13 is allowable since the prior art does not disclose about further comprising: a first transformer comprising a first input side coil and a first output side coil; a second transformer comprising a second input side coil and a second output side coil; and a phase shift circuit that is connected between an output terminal of the first peak amplifier and the first transformer, wherein a first end of the first input side coil is connected to an output terminal of the carrier amplifier, wherein a second end of the first input side coil is connected to the output terminal of the first peak amplifier with the phase shift circuit interposed between the second end of the first input side coil and the output terminal of the first peak amplifier, wherein a first end of the first output side coil is connected to an output terminal of the Doherty amplification circuit, wherein a second end of the first output side coil is connected to the second output side coil, wherein a first end of the second input side coil is connected to an output terminal of the second peak amplifier, wherein a second end of the second input side coil is connected to ground, wherein a first end of the second output side coil is connected to the second end of the first output side coil, and wherein a second end of the second output side coil is connected to ground. Claim 14 is allowable since the prior art does not disclose about further comprising: a first transformer comprising a first input side coil and a first output side coil; a second transformer comprising a second input side coil and a second output side coil; and a third transformer comprising a third input side coil and a third output side coil, wherein a first end of the first input side coil is connected to an output terminal of the carrier amplifier, wherein a second end of the first input side coil is connected to ground, wherein a first end of the first output side coil is connected to an output terminal of the Doherty amplification circuit, wherein a second end of the first output side coil is connected to the second output side coil, wherein a first end of the second input side coil is connected to an output terminal of the first peak amplifier, wherein a second end of the second input side coil is connected to ground, wherein a first end of the second output side coil is connected to the second end of the first output side coil, wherein a second end of the second output side coil is connected to the third output side coil, wherein a first end of the third input side coil is connected to an output terminal of the second peak amplifier, wherein a second end of the third input side coil is connected to ground, wherein a first end of the third output side coil is connected to the second end of the second output side coil, and wherein a second end of the third output side coil is connected to ground. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Examiner, Art Unit 2843
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Prosecution Timeline

Jul 16, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+12.5%)
2y 4m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 2248 resolved cases by this examiner. Grant probability derived from career allowance rate.

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