DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I in the reply filed on 04/22/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden to examine Invention II. This is not found persuasive because Invention II (claim 5) comprises distinguished limitations (maintaining a resistance of a serial resistive element connected to a memory element as a first resistance during a first operation of the memory element; and maintaining the resistance of the serial resistive element as a second resistance during a second operation of the memory element) that requires further search and consideration.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pramanik etal. (US 2013/0221314).
Regarding claim 1, Fig. 2A of Pramanik discloses a memory device comprising:
a memory unit [112];
a variable serial resistive element [220] connected to the memory unit [112];
a controller [150, as discloses in paragraph 0053, 150 is a read/write circuit that controls reading and writing operations. Therefore, 150 can be called a controller] connected to the variable serial resistive element [220] and configured to control a resistance of the variable serial resistive element [as shows in Fig. 2C, curve 810, the I-V relationship is non-linear. Therefore, resistance of 220 changes. Paragraphs 0056 and 0057]; and
a power source [as discloses in paragraph 053, circuit 150 provide biasing voltage to the electrode 102 and 118. Therefore, there is a power source inherent in circuit 150] connected to the variable serial resistive element [220].
Regarding claim 2, Fig. 2A of Pramanik discloses wherein the memory unit comprises a resistive memory element [112, paragraph 0052].
Regarding claim 3, Fig. 2A of Pramanik discloses wherein the memory unit comprises one of a resistive variable element [112] and a resistance change layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Pramanik etal. (US 2013/0221314) in view of Gholamipour et al. (US Pub. 2019/0108119).
Regarding claim 4, Pramanik discloses all claimed invention, but does not specifically disclose wherein the memory unit comprises a vertical NAND (VNAND) memory. However, Fig. 6 of Gholamipour discloses a resistive memory device that connected as vertical NAND [paragraph 0074].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Gholamipour’s vertical NAND string to the teachings of Pramanik’s resistive memory having resistive element such that Pramanik’s memory device arrange in compact manor according to Gholamipour’s teachings for the purpose of reducing chip space and lower power consumption.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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