DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,068,230. Although the claims at issue are not identical, they are not patentably distinct from each other because regarding claim 1, U.S. Patent No. 12,068,230 discloses in claim 1, a semiconductor module comprising: a conductive substrate having an obverse surface facing one side in a thickness direction and a reverse surface facing opposite from the obverse surface; a semiconductor element electrically bonded to the obverse surface and having a switching function; a control terminal for controlling the semiconductor element; a control terminal support disposed between the obverse surface and the control terminal and including an insulating layer; a first input terminal, a second input terminal and a third input terminal each disposed on one side with respect to the conductive substrate in a first direction perpendicular to the thickness direction; at least one output terminal disposed on an opposite side with respect to the conductive substrate in the first direction; and a sealing resin having a resin obverse surface facing a same side as the obverse surface and a resin reverse surface facing opposite from the resin obverse surface, the sealing resin covering the conductive substrate, the semiconductor element and a part of the control terminal, wherein the control terminal is exposed from the resin obverse surface as viewed in the thickness direction.
Regarding claims 2-9, U.S. Patent No. 12,068,230 discloses in claims 2-6, a semiconductor module wherein the conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other and disposed on the one side and the opposite side in the first direction, respectively, the semiconductor element includes a first semiconductor element electrically bonded to the first conductive portion and a second semiconductor element electrically bonded to the second conductive portion, the first input terminal is electrically connected to one of the first semiconductor element and the second semiconductor element, the second input terminal and the third input terminal are disposed on one side and an opposite side, respectively, with respect to the first input terminal being disposed therebetween in a second direction perpendicular to the thickness direction and the first direction, the second input terminal and the third input terminal have a polarity opposite to that of the first input terminal, and the output terminal is electrically connected to the second conductive portion; wherein the control terminal support further includes a first metal layer disposed on the insulating layer on the one side in the thickness direction and a second metal layer disposed on the insulating layer on an opposite side in the thickness direction, the second metal layer being bonded to the conductive substrate in a manner facing the obverse surface; further comprising a conductive bonding material, wherein the control terminal is bonded to the first metal layer via the conductive bonding material; further comprising a conductive wire, wherein the semiconductor element includes an element obverse surface facing a same side as the obverse surface, an element reverse surface facing opposite from the element obverse surface, and a gate electrode disposed on the element obverse surface, the conductive wire is connected to the gate electrode and the first metal layer; wherein the first semiconductor element comprises a plurality of first semiconductor elements spaced apart from each other in the second direction, and the second semiconductor element comprises a plurality of second semiconductor elements spaced apart from each other in the second direction; wherein the control terminal comprises a plurality of control terminals, and the control terminal support supports the plurality of control terminals and is disposed between the obverse surface and the plurality of control terminals; wherein the control terminal support is formed by a DBC (Direct Bonded Copper) substrate; wherein the insulating layer is made of a ceramic.
Regarding claim 10, U.S. Patent No. 12,068,230 discloses in claim 1, a semiconductor module comprising: a conductive substrate having an obverse surface facing one side in a thickness direction and a reverse surface facing opposite from the obverse surface; a semiconductor element electrically bonded to the obverse surface and having a switching function; a control terminal for controlling the semiconductor element; a control terminal support disposed between the obverse surface and the control terminal and including an insulating layer; a first input terminal, a second input terminal and a third input terminal each disposed on one side with respect to the conductive substrate in a first direction perpendicular to the thickness direction; at least one output terminal disposed on an opposite side with respect to the conductive substrate in the first direction; and a sealing resin having a resin obverse surface facing a same side as the obverse surface and a resin reverse surface facing opposite from the resin obverse surface, the sealing resin covering the conductive substrate, the semiconductor element and a part of the control terminal, wherein the control terminal is exposed from the resin obverse surface as viewed in the thickness direction, the conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other and disposed on the one side and the opposite side in the first direction, respectively, the semiconductor element includes a first semiconductor element electrically bonded to the first conductive portion and a second semiconductor element electrically bonded to the second conductive portion, the first input terminal is electrically connected to one of the first semiconductor element and the second semiconductor element, the second input terminal and the third input terminal are disposed on one side and an opposite side, respectively, with respect to the first input terminal being disposed therebetween in a second direction perpendicular to the thickness direction and the first direction, the second input terminal and the third input terminal have a polarity opposite to that of the first input terminal, and the output terminal is electrically connected to the second conductive portion, the control terminal support further includes a first metal layer disposed on the insulating layer on the one side in the thickness direction and a second metal layer disposed on the insulating layer on an opposite side in the thickness direction, the second metal layer being bonded to the conductive substrate in a manner facing the obverse surface, and the control terminal comprises a plurality of control terminals, and the control terminal support supports the plurality of control terminals and is disposed between the obverse surface and the plurality of control terminals.
Regarding claims 11-15, U.S. Patent No. 12,068,230 discloses in claim 2-13,
a semiconductor module according to claim 10, further comprising a conductive bonding material, wherein the control terminal is bonded to the first metal layer via the conductive bonding material; further comprising a conductive wire, wherein the semiconductor element includes an element obverse surface facing a same side as the obverse surface, an element reverse surface facing opposite from the element obverse surface, and a gate electrode disposed on the element obverse surface, the conductive wire is connected to the gate electrode and the first metal layer; wherein the first semiconductor element comprises a plurality of first semiconductor elements spaced apart from each other in the second direction, and the second semiconductor element comprises a plurality of second semiconductor elements spaced apart from each other in the second direction; wherein the control terminal support is formed by a DBC (Direct Bonded Copper) substrate; wherein the insulating layer is made of a ceramic.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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