DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12,080,605 (hereinafter “Pat-605”). Although the claims at issue are not identical, they are not patentably distinct from each other because Pat-605 discloses all the claimed limitations. See rejections below.
Regarding Claim 1, Pat-605 discloses an integrated circuit structure, comprising: a vertical stack of horizontal nanowires (see claim 1); a gate structure over the vertical stack of horizontal nanowires, the gate structure surrounding a channel region of each of the vertical stack of horizontal nanowires (see claim 1); a first source or drain structure laterally adjacent to a first end of the vertical stack of horizontal nanowires (see claim 1); a second source or drain structure laterally adjacent to a second end of the vertical stack of horizontal nanowires, the second end opposite the first end (see claim 1); and a backside interconnect vertically beneath and electrically coupled to one of the first source or drain structure or the second source or drain structure (see claim 1), wherein the vertical stack of horizontal nanowires is vertically overlapping with the backside interconnect (the backside interconnect has a lateral width greater than a lateral width of the one of the first source or drain structure or the second source or drain structure; see claim 1; therefore, the backside interconnect extending beyond the lateral width of the one of the first source or drain structure or the second source or drain structure is vertically overlapping with the vertical stack of horizontal nanowires).
Regarding Claim 2, Pat-605 discloses further comprising: a contact material vertically between and in contact with the backside interconnect and the one of the first source or drain structure or the second source or drain structure (see claim 2).
Regarding Claim 3, Pat-605 discloses further comprising: a second vertical stack of horizontal nanowires vertically over the vertical stack of horizontal nanowires (see claim 3).
Regarding Claim 4, Pat-605 discloses further comprising: an isolation region vertically between the second vertical stack of horizontal nanowires and the vertical stack of horizontal nanowires (see claim 4).
Regarding Claim 5, Pat-605 discloses further comprising: a second vertical stack of horizontal nanowires laterally spaced apart from the vertical stack of horizontal nanowires (see claim 5).
Regarding Claim 6, Pat-605 discloses wherein the one of the first source or drain structure or the second source or drain structure is laterally adjacent to an end of the second vertical stack of horizontal nanowires (see claim 6).
Regarding Claim 7, Pat-605 discloses wherein the one of the first source or drain structure or the second source or drain structure has a bottommost surface co-planar with a bottommost surface of the gate structure (see claim 7).
Regarding Claim 8, Pat-605 discloses wherein the one of the first source or drain structure or the second source or drain structure has an uppermost surface co-planar with an uppermost surface of the gate structure (see claim 8).
Regarding Claim 9, Pat-605 discloses wherein the one of the first source or drain structure or the second source or drain structure has a bottommost surface co-planar with a bottommost surface of the gate structure (see claim 9), and wherein the one of the first source or drain structure or the second source or drain structure has an uppermost surface co-planar with an uppermost surface of the gate structure (see claim 9).
Regarding Claim 10, Pat-605 discloses wherein the gate structure comprises a gate electrode and a gate dielectric (see claim 10).
Allowable Subject Matter
Claims 11-20 are allowed and claims 1-10 will be allowed after overcoming the nonstatutory double patenting rejections set forth above.
The closest prior art, US Pub. 2014/0001441, discloses an integrated circuit structure, comprising: a vertical stack of horizontal nanowires 106; a gate structure over the vertical stack of horizontal nanowires, the gate structure (114, 116) surrounding a channel region 108 of each of the vertical stack of horizontal nanowires 106 (fig. 1D); a first source or drain structure 115 (left one) laterally adjacent to a first end of the vertical stack of horizontal nanowires 106 (fig. 1D); a second source or drain structure 115 (right one) laterally adjacent to a second end of the vertical stack of horizontal nanowires 106 (fig. 1D), the second end opposite the first end (fig. 1D).
Another prior art, US Pub. 2011/0169083, discloses a backside interconnect 266 vertically beneath and electrically coupled to one of a first source or drain structure 216 or a second source or drain structure 216 (fig. 10).
However, both prior arts differ from the present invention because the prior arts fail to disclose the vertical stack of horizontal nanowires is vertically overlapping with the backside interconnect, nor the backside interconnect extends laterally into a backside spacer.
The following is an examiner’s statement of reasons for allowance:
Claim 1 recites a backside interconnect vertically beneath and electrically coupled to one of the first source or drain structure or the second source or drain structure, wherein the vertical stack of horizontal nanowires is vertically overlapping with the backside interconnect.
Claim 11 recites a backside interconnect vertically beneath and electrically coupled to the one of the first source or drain structure or the second source or drain structure, wherein the backside interconnect extends laterally into the backside spacer.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-10 and 12-20 variously depend from claim 1 or 11, so they are allowed or will be allowed for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 September 2, 2026
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