Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/16/2024,03/21/2025 and 10/07/2024 is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 12040288 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the scope of the claims in US 12040288 B2 teaches the scope of the claim limitations of application 18/774,379 being examined.
Attached below is a table of the claims rejected under double patenting by the claims of the parent case .
.
Claim numbering that are anticipated
Instant Application Claims
Conflicting Application/Patent Claims by Sax et al, (US 12040288 B2)
1
1. A method of manufacturing a chip package, comprising: providing a chip; forming an exposed metal region and a non-metal region on the chip; forming a metal protection layer structure over the exposed metal region and the non-metal region, the metal protection layer structure comprising a low-temperature deposited oxide; and forming a hydrothermally converted metal oxide layer over the protection layer structure.
1. A chip package, comprising: at least one chip; an exposed metal region and non-metal region; a metal protection layer structure over the exposed metal region and non-metal region, the protection layer structure comprising a low-temperature deposited oxide; and a hydrothermally converted metal oxide layer over the protection layer structure.
2
2. The method according to claim 1, wherein the low-temperature deposited oxide comprises a metal oxide.
2. The chip package according to claim 1, wherein the low-temperature deposited oxide comprises or consists of a metal oxide.
3
3. The method according to claim 1, wherein the hydrothermally converted metal oxide layer comprises an aluminum hydroxide layer.
3. The chip package according to claim 1, wherein the hydrothermally converted metal oxide layer comprises or consists of an aluminum hydroxide layer.
4
4. The method of claim 1, comprising: forming an aluminum oxide layer between the metal protection layer structure and the hydrothermally converted metal oxide layer.
4. A chip package, comprising: at least one chip; an exposed metal region and non-metal region; a metal protection layer structure over the exposed metal region and non-metal region, and configured to protect the metal region from oxidation; a hydrothermally converted metal oxide layer over the protection layer structure; and an aluminum oxide layer between the metal protection layer structure and the hydrothermally converted metal oxide layer.
5
5. The method according to claim 1, wherein the metal protection layer structure comprises a top layer comprising at least one of a group of materials, the group consisting of: silicon dioxide; titanium dioxide; zinc oxide; hafnium dioxide; tantalum pentoxide; and zirconium dioxide.
5. The chip package according to claim 1, wherein the metal protection layer structure comprises a top layer comprising at least one of a group of materials, the group consisting of: silicon dioxide; titanium dioxide; zinc oxide; hafnium dioxide; tantalum pentoxide; and zirconium dioxide.
6
6. The method according claims 5, wherein the metal protection layer structure comprises an aluminum oxide layer between the top layer and the exposed metal region.
6. The chip package according claim 5, wherein the metal protection layer structure comprises an aluminum oxide layer between the top layer and the exposed metal region.
7
7. The method according to claim 1, wherein the metal protection layer structure comprises aluminum oxide with a top layer of doped aluminum oxide.
7. The chip package according to claim 1, wherein the metal protection layer structure comprises aluminum oxide with a top layer of doped aluminum oxide.
8
8. The method according to claim 1, wherein the exposed metal region comprises at least one of a group of metal regions, the group consisting of: a chip pad; a leadframe; a wire bond; a clip; and a stripe bond.
8. The chip package according to claim 1, wherein the exposed metal region comprises at least one of a group of metal regions, the group consisting of: a chip pad; a leadframe; a wire bond; a clip; and a stripe bond
9
9. The method according to claim 1, wherein the exposed metal region comprises at least one of a group of materials, the group consisting of: copper (Cu); nickel (Ni); nickel-phosphorus (NiP); aluminum (Al); gold (Au); silver (Ag); palladium (Pd); and alloys thereof, for example PdAuAg.
9. The chip package according to claim 1, wherein the exposed metal region comprises at least one of a group of materials, the group consisting of: copper (Cu); nickel (Ni); nickel-phosphorus (NiP); aluminum (Al); gold (Au); silver (Ag); palladium (Pd); and alloys thereof, for example PdAuAg.
10
10. The method according to claim 1, further comprising: attaching an encapsulation material to at least a portion of the exposed metal region.
10. The chip package according to claim 1, further comprising: an encapsulation material attached to at least a portion of the exposed metal region by the metal protection layer structure and the hydrothermally converted metal oxide layer
11
11. The method according to claim 10, further comprising: providing a non-metal layer; and further attaching the encapsulation material to at least a portion of the non-metal layer.
11. The chip package according to claim 10, further comprising: a non-metal layer; wherein the encapsulation material is further attached to at least a portion of the non-metal layer
12
12. A method of manufacturing a chip package, comprising: providing at least one chip positioned on a leadframe surface; forming an exposed metal region and a non-metal region on a surface of the at least one chip; forming a metal protection layer structure over the exposed metal region and non-metal region, the protection layer structure comprising a metal oxide; and forming a hydrothermally converted metal oxide layer over the protection layer structure.
12. A chip package, comprising: at least one chip positioned on a leadframe surface; an exposed metal region and non-metal region on a surface of the at least one chip; a metal protection layer structure over the exposed metal region and non-metal region, the protection layer structure comprising a metal oxide; and a hydrothermally converted metal oxide layer over the protection layer structure.
13
13. The method of claim 12, wherein the metal oxide comprises an aluminum oxide
13. The chip package according to claim 12, wherein the metal oxide comprises an aluminum oxide
14
14. The method of claim 12, where the hydrothermally converted metal oxide layer comprises an aluminum hydroxide layer.
14. The chip package according to claim 12, where the hydrothermally converted metal oxide layer comprises an aluminum hydroxide layer.
15
15. The method of claim 12, where the metal protection layer structure comprises a multilayer formed by a plurality of single layers.
15. The chip package of claim 12, where the metal protection layer structure comprises a multilayer formed by a plurality of single layers.
16
16. The method of claim 15, where one or more of the plurality of single layers are made of different material.
16. The chip package of claim 15, where one or more of the plurality of single layers are made of different material.
17
17. The method of claim 12, where the metal protection layer structure is an adhesion layer structure.
17. The chip package of claim 12, where the metal protection layer structure is an adhesion layer structure.
18
18. The method of claim 12, where the metal protection layer structure includes a moisture resistant doped region that is doped with silicon.
18. The chip package of claim 12, where the metal protection layer structure includes a moisture resistant doped region that is doped with silicon.
19
19. The method of claim 12, further comprising: an encapsulation material attached to at least a portion of the exposed metal region and the non-metal region by the metal protection layer structure and the hydrothermally converted metal oxide layer.
19. The chip package of claim 12, further comprising: an encapsulation material attached to at least a portion of the exposed metal region and non-metal region by the metal protection layer structure and the hydrothermally converted metal oxide layer.
20
20. The method of claim 12, where the metal protection layer structure and the hydrothermally converted metal oxide layer extend directly over the leadframe surface.
20. The chip package of claim 12, where the metal protection layer structure and the hydrothermally converted metal oxide layer extend directly over the leadframe surface
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897
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