DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. U.S. Patent Application Publication 20210028112 A1 (the ‘112 reference, of record and matured into U.S. Patent 11,721,628 B2).
The reference discloses in Figs. 1, 2 and related text a method of fabricating an integrated circuit as claimed.
Referring to claim 18, the ‘112 reference discloses a method of fabricating an integrated circuit, the method comprising:
fabricating a set of transistors (of a logic circuit or a memory device (para [3], (paragraph(s) [0003]))) in a front-side of a substrate (101, para [48]);
depositing a first set of conductive structures (“second wiring portion ML2”, para [48], note that structures ML2 include M2’s and that Fig. 2 is a cross-sectional view of the semiconductor device illustrated in FIG. 1, para [11]) on a back-side of the substrate (101) opposite from the front-side thereby forming a set of power rails (para [50]: each of “second wiring portion[s] ML2 may provide a signal line and a power line for a plurality of elements); and
depositing a second set of conductive structures (other M2’s of ML2’s) on the back-side of the substrate (101) thereby forming a set of signal lines (para [50]: “signal line[s]”), the set of signal lines being electrically connected to the set of transistors (para [48]: “contact structure 180 connected to a plurality of elements (for example, the source/drain region 110, and the like) formed on the substrate 101 may be connected to a second wiring portion ML2 located on the rear surface of the substrate 101, via the buried conductive wiring 120 and the conductive through structure 250”).
Referring to claim 19, the ‘112 reference further discloses: depositing a third set of conductive structures (M1 of ML1, para [46]) over the set of transistors thereby forming a first metal layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 20 is rejected under 35 U.S.C. §103 as being unpatentable over Kim et al. U.S. Patent Application Publication 20210028112 A1 (the ‘112 reference) in view of Komuro U.S. Patent Application Publication 20060012639 or Fratti et al. U.S. Patent 8,859,395.
Referring to claim 20, the ‘112 reference discloses an integrated circuit comprising the substrate (101) as detailed above for claim 18 including electrodes (through structure 250, para [36]) and the set of transistors, but does not disclose performing thinning on the back-side of the substrate opposite from the front-side.
Komuro, in disclosing an integrated circuit (Fig. 1) including electrodes 12 (para [33]) through a substrate 10, teaches performing thinning on the back-side of the substrate opposite from the front-side to expose the electrodes (end of claim 1); or, Fratti, in disclosing an integrated circuit (Fig. 4) including DMOS transistor 102 (col. 1, lines 19-25) on a substrate 104, teaches performing thinning on the back-side of the substrate opposite from the front-side to reduce stress (col. 3, lines 12-32).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have performed thinning on the back-side of the substrate (101) opposite from the front-side. One would have been motivated to make such a modification in view of the teachings in Komuro to expose the electrodes (250) or in Fratti to reduce stress.
Allowable Subject Matter
4. Claims 1-17 are allowable over the prior art of record.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an integrated circuit with all exclusive limitations as recited in claims 1 and 11, which may be characterized (claim 1) in that a second conductor is on the back-side of the substrate, extends in the first direction and is separated from the first conductor in a second direction, that a first contact extends in the second direction, is electrically coupled to the second conductor and the first active region, and is located on a second level different from the first level, and in that the second conductor is electrically coupled to the first set of transistors and the second set of transistors, and (claim 11) a second conductor is on the back-side of the substrate, extends in the first direction and is separated from the first conductor in a second direction, and in that the second conductor electrically couples the first gate and the second gate together.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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08-19-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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