DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/16/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 and 5-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5-20 of U.S. Patent No. 12,052,858. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims have been patented.
Regarding claim 1, Pat '858 discloses, in claim 1, an apparatus, comprising:
a substrate including circuitry components; a stack of layers disposed on the substrate;
conductive lines extending in a first direction and located along at least one layer of the stack of layers; and conductive contacts coupled to the conductive lines to electrically couple the conductive lines to the circuitry components ("the memory device comprising: a substrate including circuitry components; a vertical stack of layers disposed on the substrate; horizontal conductive lines located along a horizontal plane in at least one layer of the vertical stack of layers; and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components", in claim 1 of Pat '858, is interpreted as the same limitation).
Regarding claim 2, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 2, a group of layers that comprises: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer ("the group of layers comprises: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer", in claim 2 of Pat '858, is interpreted as the same limitation).
Regarding claim 3, Pat '858 discloses the apparatus of claim 2 as described above.
Pat '858 further discloses, in claim 3, the conductive lines are located in the second dielectric material layer ("the horizontal conductive lines are located in the second dielectric material layer", in claim 3 of Pat '858, is interpreted as the same limitation).
Regarding claim 5, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 5, the conductive contacts directly electrically couple the conductive lines to the circuitry components in the absence of an additional interconnect ("the vertical contacts directly electrically coupled to the horizontal conductive lines to the circuitry components in the absence of an additional interconnect", in claim 5 of Pat '858, is interpreted as the same limitation).
Regarding claim 6, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 6, an electrical path between the conductive lines that are directly electrically coupled to the circuitry components is shorter than a comparative electrical path of a different device which employs at least an additional interconnect located between the conductive lines and the circuitry components ("an electrical path between the horizontal conductive lines that are directly electrically coupled to the circuitry components is shorter than a comparative electrical path of a different memory device which employs at least an additional horizontal interconnect located between the horizontal conductive lines and the circuitry components", in claim 6 of Pat '858, is interpreted as the same limitation).
Regarding claim 7, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claims 7 and 8, an insulating material adjacent to at least a portion of the conductive contacts, wherein the insulating material is selected from the group comprising: silicon oxide material, silicon nitride material, silicon oxynitride, or any combination thereof ("an insulating material adjacent to at least a portion of the vertical contacts" and “the insulating material is selected from silicon oxide material, a silicon nitride material, a silicon oxynitride, or any combination thereof”, in claims 7 and 8 of Pat '858, are interpreted as the same limitation).
Regarding claim 8, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 1, the conductive lines are located in a horizontal plane along the at least one layer of the stack of layers ("horizontal conductive lines located along a horizontal plane in at least one layer of the vertical stack of layers”, in claim 1 of Pat '858, is interpreted as the same limitation).
Regarding claim 9, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 9, the conductive lines are digit lines ("the horizontal conductive lines are digit lines”, in claim 9 of Pat '858, is interpreted as the same limitation).
Regarding claim 10, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 10, the apparatus is a three-dimensional (3D) dynamic random access memory (DRAM) device ("the memory device is a three- dimensional (3D) dynamic random access memory device”, in claim 10 of Pat '858, is interpreted as the same limitation).
Regarding claim 11, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 11, the conductive lines are configured in a staircase contact structure ("the horizontal conductive lines are configured in a staircase contact structure”, in claim 11 of Pat '858, is interpreted as the same limitation).
Regarding claim 12, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 12, the stack of layers includes an array of vertically stacked memory cells formed therein and having a number of horizontal access devices ("the array of vertically stacked memory cells further comprises a number of horizontal access devices”, in claim 12 of Pat '858, is interpreted as the same limitation).
Regarding claim 13, Pat '858 discloses the apparatus of claim 12 as described above.
Pat '858 further discloses, in claim 13, each horizontal access device of the number of horizontal access devices is directly electrically coupled, via a respective contact of the conductive contacts, to a corresponding circuitry component ("each horizontal access device of the number of horizontal access devices is directly electrically coupled, via a respective vertical contact of the vertical contacts, to a corresponding circuitry component”, in claim 13 of Pat '858, is interpreted as the same limitation).
Regarding claim 14, Pat '858 discloses the apparatus of claim 13 as described above.
Pat '858 further discloses, in claims 1 and 14, the conductive contacts are vertical contacts, and wherein a total number of the vertical contacts is equal to a total number of the number of horizontal access devices ("vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components” and “a total number of the vertical contacts is equal to a total number of the number of horizontal access devices”, in claims 1 and 14 of Pat '858, are interpreted as the same limitation).
Regarding claim 15, Pat '858 discloses, in claim 15, a method, comprising: forming a number of layers, in repeating iterations to form a vertical stack on a substrate, the number of layers comprising a dielectric material layer having multi-direction horizontal conductive lines formed along a horizontal plane therein; performing a removal process to form a contact structure; forming spaced vertical openings through the vertical stack; forming an insulating material in the spaced vertical openings; and forming vertical conductive contacts in the spaced vertical openings, wherein the vertical conductive contacts directly electrically couple the multi-direction horizontal conductive lines in the contact structure to circuitry components in the substrate ("the method comprising: forming a number of layers, in repeating iterations vertically to form a vertical stack on a substrate, the layers comprising a dielectric material layer having multi-direction horizontal conductive lines formed along a horizontal plane therein; performing a removal process to form a staircase contact structure, forming spaced, vertical openings through the vertical stack adjacent to each of the multi- direction horizontal conductive lines in the staircase contact structure; depositing an insulating material in the spaced, vertical openings; and depositing conductive material in the spaced, vertical openings to form vertical contacts to directly electrically couple the multi-direction horizontal conductive lines in the staircase contact structure to circuitry components in the substrate”, in claim 15 of Pat '858, is interpreted as the same limitation).
Regarding claim 16, Pat '858 discloses the method of claim 15 as described above.
Pat '858 further discloses, in claim 16, forming the spaced vertical openings further comprises forming the spaced vertical openings through the vertical stack ("forming the spaced, vertical openings further comprises forming the spaced, vertical openings through the vertical stack adjacent to the second portion of each of the multi-direction horizontal conductive lines in the staircase contact structure”, in claim 16 of Pat '858, is interpreted as the same limitation).
Regarding claim 17, Pat '858 discloses the method of claim 15 as described above.
Pat '858 further discloses, in claim 17, forming the spaced vertical openings further comprises forming the spaced vertical openings that extend at least along an entire respective distance between each of the multi-direction horizontal conductive lines and the substrate ("forming the spaced, vertical openings further comprises forming the spaced vertical openings that extend at least along an entire respective distance between each of the multi-direction horizontal conductive lines and the substrate”, in claim 17 of Pat '858, is interpreted as the same limitation).
Regarding claim 18, Pat '858 discloses, in claim 18, an apparatus, comprising: a vertical stack of materials on a substrate, the vertical stack of materials comprising a dielectric material having multi-directional conductive lines located therein; and vertical contacts coupled to the multi-directional conductive lines, the vertical contacts electrically coupling respective ones of the multi-directional conductive lines to corresponding circuitry components located in the substrate ("a memory device comprising: a vertical stack of materials on a substrate, the vertical stack of materials comprising a dielectric material having multi-direction horizontal conductive lines located therein, wherein each of the multi-direction horizontal conductive lines has a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction and wherein the second portions are laterally spaced to allow for vertical contacts to be coupled to the second portions; and vertical contacts coupled to the second portions of the multi-directional horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of materials to directly electrically couple respective ones of the multi-directional horizontal conductive lines to corresponding circuitry components located in the substrate”, in claim 18 of Pat '858, is interpreted as the same limitation).
Regarding claim 19, Pat '858 discloses the apparatus of claim 18 as described above.
Pat '858 further discloses, in claims 18 and 19, the multi-directional conductive lines extend in multiple horizontal directions, wherein each of the multi-directional conductive lines has a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction, and wherein the second portion is laterally spaced to allow for the vertical contacts to be coupled to the second portion and wherein the multi-directional conductive lines are horizontal digit lines or horizontal word lines ("each of the multi-direction horizontal conductive lines has a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction and wherein the second portions are laterally spaced to allow for vertical contacts to be coupled to the second portions” and “the multi-directional horizontal conductive lines are horizontal digit lines or horizontal word lines”, in claims 18 and 19 of Pat '858, are interpreted as the same limitation).
Regarding claim 20, Pat '858 discloses the apparatus of claim 19 as described above.
Pat '858 further discloses, in claim 20, the vertical stack of materials form an array of vertically stacked memory cells that are electrically coupled in an open digit line architecture or a folded digit line architecture ("the array of vertically stacked memory cells is electrically coupled in an open digit line architecture or a folded digit line architecture”, in claim 20 of Pat '858, is interpreted as the same limitation).
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,052,858 in view of claim 3 of U.S. Patent No. 11,631,681.
Regarding claim 4, Pat '858 discloses the apparatus of claim 1 as described above.
Pat '858 further discloses, in claim 1, the first direction is a horizontal direction, wherein the conductive contacts are vertical conductive contacts that extend along a vertical plane within the stack of layers ("horizontal conductive lines located along a horizontal plane in at least one layer of the vertical stack of layers; vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components", in claim 1 of Pat '858, is interpreted as the same limitation).
Pat '858 does not explicitly disclose the vertical conductive contacts are formed of a metal material.
Pat '681 teaches, in claim 3, the vertical conductive contacts are formed of a metal material ("the vertical contacts are formed of a doped semiconductor material, a conductive metal nitride, a metal, a metal-semiconductor compound, or any combination thereof", in claim 3 of Pat '681, is interpreted as the same limitation), for the purpose of providing benefits such as more density of connections between conductive lines and sense amplifiers in an interconnection area as compared to conventional structures.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in claim 1 of Pat '858 to have the vertical conductive contacts being formed of a metal material, as taught by claim 3 of Pat '681, for the purpose of providing benefits such as more density of connections between conductive lines and sense amplifiers in an interconnection area as compared to conventional structures.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-8 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2022/0216151).
Regarding claim 1, Kim discloses, in at least figures 6-7 and related text, an apparatus, comprising:
a substrate (10/30, [52]) including circuitry components (PTR/31/32/33, [52]);
a stack of layers (ST (120/EL/330), [62], [66], [67]) disposed on the substrate (10/30, [52]);
conductive lines (EL, [66]) extending in a first direction (D1, figures) and located along at least one layer of the stack of layers (ST (120/EL/330), [62], [66], [67]); and
conductive contacts (C1-C4, [89]) coupled to the conductive lines (EL, [66]) to electrically couple the conductive lines (EL, [66]) to the circuitry components (PTR/31/32/33, [52]). as described above.
Regarding claim 2, Kim discloses the apparatus of claim 1 as described above.
Kim further discloses, in at least figures 6-7 and related text, a group of layers (120/EL/330, [62], [66], [67]) that comprises:
a first dielectric material layer (120, [62]), a semiconductor material layer (material of EL, [66]), and a second dielectric material layer (330, [67]).
Regarding claim 3, Kim discloses the apparatus of claim 2 as described above.
Kim further discloses, in at least figures 6-7 and related text, the conductive lines (EL, [66]) are located in the second dielectric material layer (330, [67]).
Regarding claim 4, Kim discloses the apparatus of claim 1 as described above.
Kim further discloses, in at least figures 6-7 and related text, the first direction (D1, figures) is a horizontal direction, wherein the conductive contacts (C1-C4, [89]) are vertical conductive contacts that extend along a vertical plane within the stack of layers (ST (120/EL/330), [62], [66], [67]), and wherein the vertical conductive contacts (C1-C4, [89]) are formed of a metal material ([89]).
Regarding claim 5, Kim discloses the apparatus of claim 1 as described above.
Kim further discloses, in at least figures 6-7 and related text, the conductive contacts (C1-C4, [89]) directly electrically couple the conductive lines (EL, [66]) to the circuitry components (PTR/31/32/33, [52]) in the absence of an additional interconnect.
Regarding claim 7, Kim discloses the apparatus of claim 1 as described above.
Kim further discloses, in at least figures 6-7 and related text, an insulating material (350, [92]) adjacent to at least a portion of the conductive contacts (C1-C4, [89]), wherein the insulating material (350, [92]) is selected from the group comprising: silicon oxide material ([92]), silicon nitride material, silicon oxynitride, or any combination thereof.
Regarding claim 8, Kim discloses the apparatus of claim 1 as described above.
Kim further discloses, in at least figures 6-7 and related text, the conductive lines (EL, [66]) are located in a horizontal plane along the at least one layer of the stack of layers (ST (120/EL/330), [62], [66], [67]).
Regarding claim 11, Kim discloses the apparatus of claim 1 as described above.
Kim further discloses, in at least figures 6-7 and related text, the conductive lines (EL, [66]) are configured in a staircase contact structure (figures).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONG-HO KIM/ Primary Examiner, Art Unit 2811
Prosecution Insights