DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/16/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the barrier layer" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim because there is no previous mention of a barrier in claims 1 and 8. For examination purposes and for proper antecedence basis, the limitation is being interpreted as "the second barrier layer.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7, 9-14, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsiao et al. US PGPub. 2021/0210681. Regarding claim 1, Hsiao teaches a magnetoresistive random access memory device (100, fig. 1-2) [0015]-[0016], comprising: a cell region (129, 131, fig. 2) [0018] and a core peri region (133, fig. 2) [0018] arranged in a first horizontal direction on a substrate (202, fig. 1) [0019]; a first interlayer insulation layer (143, fig. 2) [0024] disposed on the substrate (202) in the cell region (129, 131) and the core peri region (133); a second interlayer insulation layer (139, fig. 2) [0034] disposed on the first interlayer insulation layer (143); a first wiring line (141, fig. 2) [0017] disposed in the first interlayer insulation layer (143) in the cell region (129, 131) and the core peri region (133); a lower electrode contact (127, fig. 2) [0017] disposed on the first wiring line (141) in the cell region (129, 131); and first (107, fig. 2) [0016] and second information storage structures (153, fig. 2) [0018] disposed on the lower electrode contact (127) in the cell region (129, 131), wherein each of the first (107) and second information storage structures (153) includes a lower electrode (125, fig. 2) [0016] and a magnetic tunnel junction (MTJ) structure (140, fig. 2) [0016] disposed on the lower electrode (125), wherein the first information storage structure (107) further comprises an upper electrode (111, fig. 2) [0016] disposed on the MTJ structure (140) and a first barrier layer (spacer 115, fig. 2; hereinafter called 115-129) [0016] deposited on each sidewall of the upper electrode (11), and the second information storage structure (153) further comprises a second barrier layer (spacer 115, fig. 2; hereinafter called 115-131) [0016] disposed on the MTJ structure (140) (Hsiao et al., fig. 1-2).
Regarding claim 2, Hsiao teaches the magnetoresistive random access memory device of claim 1, wherein the first barrier layer (115-129) is conformally formed along each sidewall of the upper electrode (111), and a first thickness and a second thickness of the barrier layer (115-129) deposited on each sidewall of the upper electrode (111) are equal to each other (Hsiao et al., fig. 2).
Regarding claim 4, Hsiao teaches the magnetoresistive random access memory device of claim 1, wherein the second information storage structure (153) is disposed adjacent to the core peri region(133) in the cell region (131) (Hsiao et al., fig. 2).
Regarding claim 5, Hsiao teaches the magnetoresistive random access memory device of claim 1, wherein a height (110, fig. 2) [0019] of the first information storage structure (107) in a vertical direction is greater than (fig. 2, [0019]) a height (114, fig. 2) [0019] of the second information storage structure (153) in a vertical direction (Hsiao et al., fig. 2, [0019]).
Regarding claim 7, Hsiao teaches the magnetoresistive random access memory device of claim 1, wherein a height of the second barrier layer (115-131) is not greater than a height of the upper electrode (111) (Hsiao et al., fig. 2).
Regarding claim 9, Hsiao teaches the magnetoresistive random access memory device of claim 1, wherein the first barrier layer (115-129) and the second barrier layer (115-131) comprise substantially a same material (Hsiao et al., fig. 2, [0042]).
Regarding claim 10, Hsiao teaches the magnetoresistive random access memory device of claim 1, wherein the lower electrode contact (127) is in contact (direct contact, fig. 2) with the first wiring line (141) (Hsiao et al., fig. 2).
Regarding claim 11, Hsiao teaches the magnetoresistive random access memory device of claim 1, wherein the lower electrode contact (127) passes through the second interlayer insulation layer (139) (Hsiao et al., fig. 2).
Regarding claim 12, Hsiao teaches a magnetoresistive random access memory device (100, fig. 1-2) [0015]-[0016], comprising: a cell region (129, 131, fig. 2) [0018] and a core peri region (133, fig. 2) [0018] arranged in a first horizontal direction on a substrate (202, fig. 1) [0019]; a lower conductive region (118/217, fig. 2) [0023] disposed in the cell region (129, 131) and the core peri region (133); a first wiring structure (141, fig. 2) [0017] that is connected to the lower conductive region (217) in the cell region (129, 131) and the core peri region (133); a lower electrode contact (127, fig. 2) [0017] connected to the first wiring structure (141) in the cell region (129, 131); and a first information storage structure (107, fig. 2) [0016] disposed on the lower electrode contact (127), wherein the first information storage structure (107) includes a lower electrode (125, fig. 2) [0016] disposed on the lower electrode contact (127), a magnetic tunnel junction (MTJ) structure (140, fig. 2) [0016] disposed on the lower electrode (125), and an upper electrode (111, fig. 2) [0016] spaced apart from the lower electrode (125) with the MTJ structure (140) interposed therebetween, wherein the first information storage structure (107) further comprises a first barrier layer (spacer 115, fig. 2; hereinafter called 115-129) [0016] conformally disposed on both sidewalls of the upper electrode (111) (Hsiao et al., fig. 1-2). Regarding claim 13, Hsiao teaches the magnetoresistive random access memory device of claim 12, further comprising at least one second information storage structure (153, fig. 2) [0018] disposed in a region between the first information storage structure (107) and a boundary portion (131, fig. 2) between the cell region (129) and the core peri region (133), in the cell region (129, 131), wherein the at least one second information storage structure (153) comprises a lower electrode (125, fig. 2) [0016], an MTJ structure (140, fig. 2) [0016] disposed on the lower electrode (125), and a second barrier layer (spacer 115, fig. 2; hereinafter called 115-131) [0016] disposed on the MTJ structure (140) (Hsiao et al., fig. 2).
Regarding claim 14, Hsiao teaches the magnetoresistive random access memory device of claim 13, wherein a height of the at least one second information storage structure (153) is not greater than a height of the first information storage structure (107) (Hsiao et al., fig. 2).
Regarding claim 17, Hsiao teaches the magnetoresistive random access memory device of claim 13, wherein a height of the second barrier layer (115-131) is not greater than a height of the upper electrode (111) (Hsiao et al., fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US PGPub. 2021/0210681 as applied to claim 1 above, and further in view of Iwayama et al. US PGPub. 2015/0069547. Regarding claim 3, Hsiao does not teach the magnetoresistive random access memory device of claim 1, wherein a thickness of the first barrier layer (115-129) in the first horizontal direction does not exceed 3 nm. However, Iwayama teaches a magnetoresistive random access memory device (fig. 6) [0009] wherein a thickness (t1, fig. 6) of the first barrier layer (119A, fig. 6) [0049] in the first horizontal direction does not exceed 3 nm (t1 is 3nm-10nm) [0081] (Iwayama et al., fig. 6, [0081]). Accordingly, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to combine the teaching of Hsiao with that of Iwayama such that the thickness of the first barrier is in the range as claimed in order to provide a magnetic memory with improved reliability and manufacturing yield (Iwayama et al., [0095]), because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US PGPub. 2021/0210681 as applied to claim 1 above, and further in view of Huang et al. US PGPub. 2017/0294576.
Regarding claim 6, Hsiao does not teach the magnetoresistive random access memory device of claim 1, wherein the first barrier layer (115-129) and the second barrier layer (115-131) each comprise titanium oxide. Hsiao teaches that the first and second barrier (115) as SiN [0042]. However, Huang teaches a magnetoresistive random access memory device (200, fig. 13) [0031] wherein the first barrier layer (spacer 950, fi. 13) [0040] and the second barrier layer (spacer 950, fi. 13) [0040] each comprise titanium oxide [0040] (Huang et al., fig. 13, [0040]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitute of the SiN of Hsiao with the TiO2 of Huang because SiN and TiO2 (Huang et al., [0040]) are well known alternatives in the art and such substitution is art recognized equivalence for the same purpose to obtain predictable results (see MPEP 2144.06).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US PGPub. 2021/0210681 as applied to claim 12 above, and further in view of Iwayama et al. US PGPub. 2015/0069547 and Huang et al. US PGPub. 2017/0294576.
Regarding claim 15, Hsiao teaches the magnetoresistive random access memory device of claim 12, wherein the upper electrode (111) comprises titanium nitride [0029] but fail to teach wherein the first barrier layer (115-129) comprises titanium oxide and a thickness of the first barrier layer (115-129) does not exceed 3 nm. However, Huang teaches a magnetoresistive random access memory device (200, fig. 13) [0031] wherein the first barrier layer (spacer 950, fi. 13) [0040] comprises titanium oxide [0040] (Huang et al., fig. 13, [0040]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitute of the SiN of Hsiao with the TiO2 of Huang because SiN and TiO2 (Huang et al., [0040]) are well known alternatives in the art and such substitution is art recognized equivalence for the same purpose to obtain predictable results (see MPEP 2144.06). But Hsiao and Huang still do not teach wherein a thickness of the first barrier layer (115-129) does not exceed 3 nm. However, Iwayama teaches a magnetoresistive random access memory device (fig. 6) [0009] wherein a thickness (t1, fig. 6) of the first barrier layer (119A, fig. 6) [0049] does not exceed 3 nm (t1 is 3nm-10nm) [0081] (Iwayama et al., fig. 6, [0081]). Accordingly, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to combine the teaching of Hsiao with that of Iwayama such that the thickness of the first barrier is in the range as claimed in order to provide a magnetic memory with improved reliability and manufacturing yield (Iwayama et al., [0095]), because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US PGPub. 2021/0210681 as applied to claim 12 above, and further in view of Chuang et al. US PGPub. 2022/0093684.
Regarding claim 16, Hsiao does not teach the magnetoresistive random access memory device of claim 12, wherein the upper electrode (111) has a trapezoid shape whose width in the first horizontal direction progressively increases toward the substrate (202), and the first barrier layer (115-129) has a profile inclined along a side surface of the upper electrode (111). However, Chuang teaches magnetoresistive random access memory device (fig. 2 and 5B) wherein the upper electrode (256, fig. 5B) [0023] has a trapezoid shape whose width in the first horizontal direction progressively increases toward the substrate (206, fig. 2) [0020], and the first barrier layer (260, fig. 5B) [0023] has a profile inclined along a side surface of the upper electrode (256) (Chuang et al., fig. 2 and 5B). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the shape of the upper electrode of Hsiao with that of Chuang because the trapezoidal shape of the upper electrode is well known in the art and such structure is art recognized and suitable for the intended purpose of reducing misalignment/improving alignment (Chuang et al., [0039]) (see MPEP 2144.07).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US PGPub. 2021/0210681 in view of Huang et al. US PGPub. 2017/0294576.
Regarding claim 18, Hsiao teaches a magnetoresistive random access memory device (100, fig. 1-2) [0015]-[0016] comprising: a cell region (129, 131, fig. 2) [0018] and a core peri region (133, fig. 2) [0018] arranged in a first horizontal direction on a substrate (202, fig. 1) [0019]; lower conductive region (118/217, fig. 2) [0023] disposed in the cell region (129, 131) and the core peri region (133); first wiring structure (141, fig. 2) [0017] that is connected to the lower conductive region (217) in the cell region (129, 131) and the core peri region (133); an interlayer insulation layer (143, fig. 2) [0024] disposed on the substrate (202) in the cell region (129, 131) and the core peri region (133); wiring lines (141, fig. 2) [0017] that pass through the interlayer insulation layer (143) and are connected to the lower conductive region (217) in the cell region (129, 131) and the core peri region (133); a lower electrode contact (127, fig. 2) [0017] disposed on the wiring lines (141); a first information storage structure (107, fig. 2) [0016] disposed on a first portion (129, fig. 2) of the lower electrode contact (128), wherein the first information storage structure (107) includes a lower electrode (125, fig. 2) [0016], a magnetic tunnel junction (MTJ) structure (140, fig. 2) [0016], and an upper electrode (111, fig. 2) [0016] that are sequentially stacked; a second information storage structure (153, fig. 2) [0018] disposed on a second portion (131, fig. 2) of the lower electrode contact (127), wherein the second information storage structure (153) includes a lower electrode (125, fig. 2) [0016], an MTJ structure (140, fig. 2) [0016], and an upper barrier layer (spacer 115, fig. 2; hereinafter called 115-131) [0016] that are sequentially stacked; and a barrier layer (spacer 115, fig. 2; hereinafter called 115-129) [0016] is conformally formed along each sidewall of the upper electrode (111) of the first information storage structure (107), wherein a vertical level of the wiring lines (141) in the cell region (129, 131) and the core peri region (133) is lower than or coplanar with a vertical level of a lower surface of the MTJ structure (140) (Hsiao et al., fig. 2). But Hsiao does not teach wherein the barrier layer (spacer 115, fig. 2; hereinafter called 115-129) [0016] that includes titanium oxide. However, Huang teaches a magnetoresistive random access memory device (200, fig. 13) [0031] wherein the barrier layer (spacer 950, fi. 13) [0040] includes titanium oxide [0040] (Huang et al., fig. 13, [0040]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitute of the SiN barrier of Hsiao with the TiO2 barrier of Huang because SiN and TiO2 (Huang et al., [0040]) are well known alternatives in the art and such substitution is art recognized equivalence for the same purpose to obtain predictable results (see MPEP 2144.06). Regarding claim 19, Hsiao in view of Huang teaches the magnetoresistive random access memory device of claim 18, wherein the second information storage structure (153) is disposed in the cell region (131, fig. 2) adjacent to the core peri region (133), and a height of the second information storage structure (153) is not greater than a height of the first information storage structure (107) (Hsiao et al., fig., 2).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hsiao et al. US PGPub. 2021/0210681 in view of Huang et al. US PGPub. 2017/0294576 as applied to claim 18 and further in view of Iwayama et al. US PGPub. 2015/0069547.
Regarding claim 20, Hsiao and Huang does not teach the magnetoresistive random access memory device of claim 18, wherein a conformal thickness of the barrier layer does not exceed 3 nm.
However, Iwayama teaches a magnetoresistive random access memory device (fig. 6) [0009] wherein a conformal thickness (t1, fig. 6) of the barrier layer (119A, fig. 6) [0049] does not exceed 3 nm (t1 is 3nm-10nm) [0081] (Iwayama et al., fig. 6, [0081]). Accordingly, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to combine the teaching of Hsiao with that of Iwayama such that the thickness of the first barrier is in the range as claimed in order to provide a magnetic memory with improved reliability and manufacturing yield (Iwayama et al., [0095]), because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Allowable Subject Matter
Claim 8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a magnetoresistive random access memory device wherein “the second barrier layer entirely covers an upper surface of the MTJ structure in the second information storage structure” as recited in claim 8 in combination with the rest of the limitations of claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin et al. US PGPub. 2022/0271087 teaches a magnetoresistive random access memory device (10, fig. 1) comprising a barrier layer on the MTJ and upper electrode.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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