DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed May 18, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 11 and 19 have been amended. No claims have been added. No new matter has been added.
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed February 20, 2026.
Information Disclosure Statement
An Information Disclosure Statement has not been entered. Applicant is reminded of the duty to disclose material information under 37 CFR 1.56. If applicant wishes to have an Information Disclosure Statement made of record, please submit form PTO/SB/08, along with any statements and fees required by 37 CFR 1.97, prior to or along with the payment of the issue fee.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari).
Regarding Independent Claim 19, Harari discloses a system, comprising:
one or more memory devices (A controller 130 operable to couple to at least one memory device, NAND flash Device 120A: Harari, Figure 6A);
a plurality of first terminals (Coupled with first terminals 144: Harari, Figure 6A);
a plurality of second terminals (Coupled with second terminals 142: Harari, Figure 6A);
a memory system controller coupled with the one or more memory devices and with the plurality of second terminals (NAND controller 130: Harari, Figure 6A); and
memory interface circuitry coupled with the one or more memory devices and with the plurality of first terminals (NAND controller 130: Harari, Figure 6A),
the memory interface circuitry comprising a buffer and configured to:
receive, via the plurality of first terminals (Receiving data through Host Side Interface 144: Harari, Figure 6A),
a command to configure the memory interface circuitry to receive data associated with a write burst (Data sent to interface circuitry 130: Harari, col.12:23-33);
receive, via the plurality of first terminals during a first duration (Receiving data through Host Side Interface 144: Harari, Figure 6A),
a first portion of the data to write to the buffer (A first portion of data, including address bytes and data bytes: Harari, col.12:32-35);
receive, via the plurality of first terminals during a second duration after the first duration (The second ECC data is received after the first data: Harari, col.12:40-43), a second portion of the data to write to the buffer (Controller 130 receives the second portion of the data from ECC module 132: Harari, col.12:42-43); and
output the first portion of the data and the second portion of the data (Outputting data through the NAND interface 142: Harari, Figure 6A) from the buffer concurrently to at least one of the one or more memory devices based at least in part on determining that an amount of data written to the buffer satisfies a threshold (Write command issued including command bytes, address bytes, first (host) data bytes, and corresponding ECC parity bits, implying that without this minimum data the write cannot take place: Harari, col.12:46-49).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 and 7-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari) in view of US 8,953,396 B2 to Ebrahim Abedifard (hereafter Abedifard).
Regarding Independent Claim 1, Harari discloses a memory system, comprising:
memory interface circuitry (NAND controller 130: Harari, Figure 6A)
operable to couple with one or more memory devices (Operable to couple to at least one memory device, NAND flash Device 120A: Harari, Figure 6A); and
processing circuitry
coupled with the memory interface circuitry (Controller Electronic Circuitry 135: Harari, Figure 6A) and
configured to cause the memory system to (Controller 130 configured to interface with the Host Device and the NAND memory: Harari, col.11:20-22):
receive, at the memory interface circuitry (Receiving at the NAND Controller 130: Harari, col.12:40),
a command via a plurality of first terminals
to configure the memory interface circuitry to receive data associated with a write burst (Controller receiving data associated with a write command: Harari, col.12:40),
the plurality of first terminals associated with a first quantity of terminals (A plurality of terminals is inherently associated with a quantity of terminals);
write a first portion of the data (A first portion of data, including address bytes and data bytes: Harari, col.12:32-35) to a buffer of the memory interface circuitry (Data sent to interface circuitry 130: Harari, 12:23-33)
based at least in part on receiving the first portion of the data (Controller 130 responds to receiving the first data: Harari, col.12:40-41)
via the plurality of first terminals (Receiving data through Host Side Interface 144: Harari, Figure 6A)
during a first duration (The first data is received during a first duration, as demonstrated by other events occurring ‘after’ receiving the first data: Harari, col.12:40-42);
write a second portion of the data to the buffer of the memory interface circuitry
based at least in part on receiving the second portion of the data (Controller 130 receives the second portion of the data from ECC module 132: Harari, col.12:42-43)
via the plurality of first terminals (Receiving data through Host Side Interface 144: Harari, Figure 6A)
during a second duration that is after the first duration (The second ECC data is received after the first data: Harari, col.12:40-43); and
output, from the buffer via a plurality of second terminals (Outputting data through the NAND interface 142: Harari, Figure 6A),
the first portion of the data and the second portion of the data to the one or more memory devices (The first and second data are output from Controller 130: Harari, col.12:46-49)
based at least in part on determining that an amount of data written to the buffer satisfies a threshold (Write command issued including command bytes, address bytes, first (host) data bytes, and corresponding ECC parity bits, implying that without this minimum data the write cannot take place: Harari, col.12:46-49).
Harari does not disclose the plurality of second terminals associated with a second quantity of terminals is greater than the first quantity of terminals. Abedifard, however, teaches a memory system wherein the plurality of second terminals associated with a second quantity of terminals is greater than the first quantity of terminals (Disclosing combining multiple input data pins, such as write enable, read enable, address latch enable, and so forth, onto a single pin, reducing the required number of input pins will leaving output pin count unaffected: Abedifard, col.2:20-64).
Abedifard teaches that reducing the number of pins reduces overall power consumption (Abedifard, col.2:25-27). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the the low-power, reduced pin count of Abedifard with the data interface controller logic of Harari, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2, Abedifard discloses the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
receive, at the memory interface circuitry (A signal sent to the memory interface: Abedifard, col.3:24-25),
a second command via the plurality of first terminals (Transmitting the signal through the SCA pin: Abedifard, col.3:26)
to write an indication of the one or more memory devices (The signal including a start instruction and a device designator: Abedifard, col.3:27-32); and
write the indication of the one or more memory devices to the memory interface circuitry
based at least in part on receiving the second command (The writing operation waiting for the start condition: Abedifard, col.4:39-41),
wherein transferring the first portion of the data and the second portion of the data is based at least in part on writing the indication (The operation requiring a start signal: Abedifard, col.3:59-61).
Regarding Claim 7, Abedifard discloses the memory system of claim 1, wherein
the first portion of the data and the second portion of the data are output concurrently via the plurality of second terminals (Data is output through output pins: Abedifard, col.3:48-51).
Regarding Claim 8, Harari discloses the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
receive, at the memory interface circuitry via the plurality of first terminals (Controller 130 received a read command: Harari, col.12:60-63),
a second command to read the data from the one or more memory devices (The command being a read command: Harari, col.12:60-63);
receive, via the plurality of second terminals based at least in part on receiving the second command (In response to the read command, reading the data: Harari, col.13.1-5),
the first portion of the data and the second portion of the data from the one or more memory devices (The controller retrieving the data from memory: Harari, col.13:7-11);
output, during a third duration, the first portion of the data via a subset of the plurality of first terminals (Outputting a first set of data: Harari, col.13:19-21); and
output, during a fourth duration after the third duration, the second portion of the data via the subset of the plurality of first terminals (Outputting the second set of data: Harari, col.13:21-24; Note, the data is specifically sent in a series, inherently disclosing a sequential return of read data).
Regarding Claim 9, Abedifard discloses the memory system of claim 8, wherein the processing circuitry is further configured to cause the memory system to:
output, during the third duration and during the fourth duration (During a read operation: Abedifard, col.3:52-54),
a clock signal (Disclosing a clock signal: Abedifard, col.3:36)
via a second subset of the plurality of first terminals that are exclusive of the second subset (The system clock signal being disabled and data read through timing of CE pin: Abedifard, col.3:35-51).
Regarding Claim 10, Harari discloses the memory system of claim 1, wherein outputting the first portion of the data and the second portion of the data is configured to cause the memory system to:
output the first portion of the data and the second portion of the data from the buffer (Outputting the read data: Harari, col.20:52-53)
to a respective controller of each of the one or more memory devices (Read data sent to the host controller: Harari, col.20:55-56).
Regarding Claim 11, Harari discloses the memory system of claim 1, wherein the one or more memory devices comprises a plurality of memory devices, and wherein outputting the first portion of the data and the second portion of the data is configured to cause the memory system to:
output the first portion of the data and the second portion of the data from the buffer (Outputting the read data: Harari, col.20:52-53)
to a first memory device of the plurality of memory devices (The data transferred to the host device: Harari, col.20:55-56) and
to a second memory device of the plurality of memory devices (Data may further be controlled upon output: Harari, col.20:66-67).
Regarding Claim 12, Abedifard discloses the memory system of claim 1, wherein
a bus of the memory interface circuitry comprises
the plurality of first terminals, one or more third terminals, and a fourth terminal (The bus including a series of terminals: Abedifard, col.3:4-10), and
the plurality of first terminals are associated with communicating commands, addresses, and data (First pins associated with input/output data: Abedifard, col.3:6),
the one or more third terminals are associated with communicating an indication of the one or more memory devices (Terminals associated with data write destination: Abedifard, col.3:8), and
the fourth terminal is associated with communicating a clock signal (Terminal associated with the clock signal: Abedifard, col.3:7).
Regarding Claim 13, Harari discloses the memory system of claim 1, wherein
the plurality of first terminals is associated with a separate command address (SCA) interface (A first set of terminals associated with the Host Side interface: Harari, Figure 3B) and
the plurality of second terminals is associated with an open NAND flash interface (ONFI) (A second set of terminals associated with the NAND memory interface: Harari, Figure 3B).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari) and US 8,953,396 B2 to Ebrahim Abedifard (hereafter Abedifard) in view of US 2013/0262744 A1 to Venkatesh Ramachandra, et al. (hereafter Ramachandra).
Regarding Claim 3, Abedifard discloses the memory system of claim 2, wherein the processing circuitry is further configured communicate with two or more different memory devices, thereby implying a signal to differentiate between them (Abedifard, col.4:55-58), although the mechanism is not made explicit. Ramachandra, however, expressly discloses a memory system as in Claim 2, wherein the processing circuitry is further configured to cause the memory system to:
receive, at the memory interface circuitry (The memory controller chip receiving an instruction: Ramachandra, ¶[0051]),
the indication of the one or more memory devices (Specifically selecting one or more of the memory devices: Ramachandra, ¶[0051])
via one or more third terminals exclusive of the plurality of first terminals (Via an exclusive terminal CEn: Ramachandra, ¶[0051]),
wherein writing the indication of the one or more memory devices is based at least in part on receiving the indication of the one or more memory devices (Entering the write mode based, at least in part, on receiving an appropriate signal on the Chip Enable input: Ramachandra, ¶[0051]).
Ramachandra teaches the use of a CEn input allows specific addressing in a multichip arrangement when otherwise reducing the number of control channels and power requirements is prioritized (Ramachandra, ¶¶[0050-51]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the dedicated chip enable input of Ramachandra with the multichip configuration of Abedifard and the data interface controller logic of Harari, with a reasonable expectation of success. The inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari) and US 8,953,396 B2 to Ebrahim Abedifard (hereafter Abedifard) in view of US 2014/0359200 A1 to Eugene Jinglun Tam (hereafter Tam).
Regarding Claim 4, Harari discloses the memory system of claim 1, but fails to explicitly disclose the further limitations of Claim 4. Abedifard teaches the interface circuitry receiving a second command via the plurality of first terminals (Transmitting the signal through the SCA pin: Abedifard, col.3:26) but does not teach the further limitations of Claim 4. Tam, however, discloses a memory system as in Claim 1, wherein the processing circuitry is further configured to cause the memory system to:
receive, at the memory interface circuitry (Describing a chip capable of operating in an active, pass-through, or stand-by mode. A command capable of shifting between modes is inherent in such a design: Tam, ¶[0035])
a command to enable a mapping associated with a header cycle type of the command and one or more functions of the memory interface circuitry (The command implementing command over chips further along the tree from the initial controller: Tam, ¶[0038]),
wherein receiving the command is based at least in part on enabling the mapping (Receiving the command and enabling the mapping linked: Tam, ¶[0037]).
Tam teaches using a control command to shift between active and pass-through modes of a circuit can significantly reduce the amount of capacitive loading on the pins (Tam, ¶[0037]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the mode shifting commands of Tam with the reduced pin count of Abedifard, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari) and US 8,953,396 B2 to Ebrahim Abedifard (hereafter Abedifard) in view of US 2004/0027881 A1 to Hideyuki Furukawa (hereafter Furukawa).
Regarding Claim 5, Abedifard teaches the interface circuitry receiving a second command via the plurality of first terminals (Transmitting the signal through the SCA pin: Abedifard, col.3:26) but does not teach the further limitations of Claim 5. Furukawa, however, discloses a memory system as in claim 1, wherein the processing circuitry is further configured to cause the memory system to:
receive, at the memory interface circuitry (Receiving a query from command controller 118: Furukawa, ¶[0040])
a second command to determine whether the buffer is empty (The query checking whether the buffer status register indicates cleared register: Furukawa, ¶[0040]); and
output an indication that the buffer is empty (Indicating the register is cleared: Furukawa, ¶[0040])
based at least in part on transferring the first portion of the data and the second portion of the data and in response to receiving the second command (Setting the buffer status register to ‘1’ following writing stored data to memory: Furukawa, ¶[0038]).
Furukawa teaches the use of a buffer status register helps reduce processing steps and time required for the write operation (Furukawa, ¶[0050]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the buffer register of Furukawa with the reduced pin count of Abedifard, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 6, Furukawa discloses the memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to:
determine that the buffer is empty (Indicating the buffer is empty: Furukawa, ¶[0040])
based at least in part on outputting the first portion of the data and the second portion of the data (Setting the buffer status register to ‘1’ following writing stored data to memory: Furukawa, ¶[0038]); and
set a value of a flag of the memory interface circuitry based at least in part on the determining (Setting the value of the buffer status register: Furukawa, ¶[0038]),
wherein the indication that the buffer is empty comprises the value of the flag (The buffer status register indicating the availability of the buffer: Furukawa, ¶[0035]).
Claim(s) 14 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari) and US 8,953,396 B2 to Ebrahim Abedifard (hereafter Abedifard) in view of US 5,369,648 to Robert W. Nelson (hereafter Nelson).
Regarding Independent Claim 14, Harari discloses a memory system, comprising:
memory interface circuitry (NAND controller 130: Harari, Figure 6A) operable to couple with one or more memory devices (Operable to couple to at least one memory device, NAND flash Device 120A: Harari, Figure 6A); and
processing circuitry coupled with the memory interface circuitry (Controller Electronic Circuitry 135: Harari, Figure 6A) and configured to cause the memory system to (Controller 130 configured to interface with the Host Device and the NAND memory: Harari, col.11:20-22):
receive, at the memory interface circuitry (Receiving at the NAND Controller 130: Harari, col.12:40),
to write an indication of the one or more memory devices (Controller receiving data associated with a write command: Harari, col.12:40),
the plurality of first terminals associated with a first quantity of terminals (A plurality of terminals is inherently associated with a quantity of terminals);
receive, at the memory interface circuitry (Receiving a first command from the host device: Harari, col.12:23-33);
write a first portion of the data sequence to a buffer of the memory interface circuitry Data sent to interface circuitry 130: Harari, 12:23-33)
based at least in part on generating the data sequence (Controller 130 responds to receiving the first data: Harari, col.12:40-41);
output, from the buffer via a plurality of second terminals (Outputting data through the NAND interface 142: Harari, Figure 6A),
the first portion of the data sequence to the one or more memory devices (The data are output from Controller 130: Harari, col.12:46-49) based at least in part on determining that an amount of data written to the buffer satisfies a threshold (Write command issued including command bytes, address bytes, first (host) data bytes, and corresponding ECC parity bits, implying that without this minimum data the write cannot take place: Harari, col.12:46-49).
Harari does not expressly disclose combining multiple input data pins into a plurality of first terminals. Abedifard, however, discloses a first command via a plurality of first terminals (Disclosing combining multiple input data pins, such as write enable, read enable, address latch enable, and so forth, onto a single pin, reducing the required number of input pins will leaving output pin count unaffected: Abedifard, col.2:20-64).
Abedifard teaches that reducing the number of pins reduces overall power consumption (Abedifard, col.2:25-27). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the the low-power, reduced pin count of Abedifard with the data interface controller logic of Harari, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Neither Harari nor Abedifard disclose writing the indication of the one or more memory devices to the memory interface circuitry based at least in part on receiving the first command nor receiving a second command via the plurality of first terminals to configure the memory interface circuitry to generate a data sequence based at least in part on writing the indication or to write a second portion of the data sequence to the buffer based at least in part on generating the data sequence and transferring the first portion.
Nelson, however, discloses a memory system wherein:
write the indication of the one or more memory devices to the memory interface circuitry based at least in part on receiving the first command (Receiving an initial seed value: Nelson, col.8:18-20)
at the memory interface circuitry, receiving
a second command via the plurality of first terminals to configure the memory interface circuitry (In response to a host device signal: Nelson, col.3:35-36)
to generate a data sequence based at least in part on writing the indication (Generating a data sequence based on the initial seed value: Nelson, col.8:7-10);
write a second portion of the data sequence to the buffer based at least in part on generating the data sequence and transferring the first portion (Disclosing generating data for a set number of cycles, implying transferring the first data and replacing with additional data: Nelson, col.7:42-50).
Nelson teaches the inclusion of circuitry capable of generating and sending pseudo-random test patterns considerably reduces the number of test patterns needed to test a device, thereby contributing to simpler and most cost effective integrated circuits (Nelson, col.1:24-33). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the internal pseudo-random logic of Nelson with the data interface controller logic of Harari, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Harari discloses the memory system of claim 14, wherein the processing circuitry is further configured to cause the memory system to:
receive, at the memory interface circuitry via the plurality of first terminals (Receiving a read command: Harari, col.20:45),
a third command to perform an error evaluation of at least one of the one or more memory devices (Checking for errors in the data: Harari, col.19:66-20:1);
perform the error evaluation of the at least one of the one or more memory devices (Checking for errors in the data: Harari, col.19:66-20:1)
based at least in part on reading the data sequence from the at least one of the one or more memory devices (The error check based on transmitted data: Harari, col.19:63-64); and
output a response to the third command based at least in part on performing the error evaluation (Responding when identified errors exceed a set threshold: Harari, col.25:35-39).
Regarding Claim 18, Nelson discloses the memory system of claim 17, wherein performing the error evaluation is configured to cause the memory system to:
generate a second data sequence based at least in part on a seed value (Teaching recreating pseudo-random data based on a seed value: Nelson, col.8:1-5); and
compare the second data sequence with the data sequence read from the at least one of the one or more memory devices to determine an error rate (Comparing read value to identify errors: Harari, col.20:56-58),
wherein generating the data sequence is based at least in part on the seed value (Basing the pseudo-random data on the initial seed value: Nelson, col.8:7:10).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari), US 8,953,396 B2 to Ebrahim Abedifard (hereafter Abedifard), and US 5,369,648 to Robert W. Nelson (hereafter Nelson) in view of US 2014/0359200 A1 to Eugene Jinglun Tam (hereafter Tam).
Regarding Claim 15, Abedifard teaches the memory system of Claim 14, wherein the interface circuitry receives a second command via the plurality of first terminals (Transmitting the signal through the SCA pin: Abedifard, col.3:26) but does not teach the further limitations of Claim 15. Tam, however, discloses a memory system as in Claim 14, wherein the processing circuitry is further configured to cause the memory system to
receive, at the memory interface circuitry via the plurality of first terminals (Describing a chip capable of operating in an active, pass-through, or stand-by mode. A command capable of shifting between modes is inherent in such a design: Tam, ¶[0035]),
a third command to enable a mapping associated with a header cycle type of the second command (The command implementing command over chips further along the tree from the initial controller: Tam, ¶[0038]) and
one or more functions of the memory interface circuitry (The command implementing command over chips further along the tree from the initial controller: Tam, ¶[0038]),
wherein receiving the second command is based at least in part on enabling the mapping (Receiving the command and enabling the mapping linked: Tam, ¶[0037]).
Tam teaches using a control command to shift between active and pass-through modes of a circuit can significantly reduce the amount of capacitive loading on the pins (Tam, ¶[0037]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the mode shifting commands of Tam with the reduced pin count of Abedifard, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari), US 8,953,396 B2 to Ebrahim Abedifard (hereafter Abedifard), and US 5,369,648 to Robert W. Nelson (hereafter Nelson) in view of US 2004/0027881 A1 to Hideyuki Furukawa (hereafter Furukawa).
Regarding Claim 16, Abedifard discloses the memory system of claim 14, wherein the interface circuitry receives an additional command via the plurality of first terminals (Transmitting the signal through the SCA pin: Abedifard, col.3:26) but does not teach the further limitations of Claim 16. Furukawa, however, teaches a memory system as in Claim 14 wherein the processing circuitry is further configured to cause the memory system to:
receive, at the memory interface circuitry via the plurality of first terminals (Receiving a query from command controller 118: Furukawa, ¶[0040]),
a third command to determine whether the data sequence was stored to the one or more memory devices (The query checking whether the buffer status register indicates cleared register, showing the write operation was effective: Furukawa, ¶[0040]); and
outputting, from the memory interface circuitry via the plurality of first terminals (Indicating the register is cleared: Furukawa, ¶[0040]),
an indication that the data sequence be stored in response to receiving the third command (Setting the buffer status register to ‘1’ following writing stored data to memory: Furukawa, ¶[0038]).
Furukawa teaches the use of a buffer status register helps reduce processing steps and time required for the write operation (Furukawa, ¶[0050]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the buffer register of Furukawa with the reduced pin count of Abedifard, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 8,291,295 B2 to Eliyahou Harari, et al. (hereafter Harari) in view of US 2014/0359200 A1 to Eugene Jinglun Tam (hereafter Tam).
Regarding Claim 20, Harari discloses the system of claim 19, but fails to disclose the further limitations of claim 20. Tam, however, discloses as system as in Claim 19, wherein the memory interface circuitry
is configured to bypass the memory system controller for communicating with the one or more memory devices (Disclosing a pass-through capable controller: Tam, ¶[0036]).
Tam teaches using a control command to shift between active and pass-through modes of a circuit can significantly reduce the amount of capacitive loading on the pins (Tam, ¶[0037]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the mode shifting commands of data interface controller logic of Harari, with a reasonable expectation of success. Both inventions are well known in the field of host/memory interface controllers and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed May 18, 2026 have been fully considered but they are not persuasive.
Applicant argues the rejection of Claim 19 under 35 U.S.C. § 102 is improper because the cited prior art Harari fails to anticipate all limitations of Claim 19, specifically the memory interface circuitry does not receive via the first terminals the first and second data to be written to the buffer (Applicant Arguments/Remarks, page 11, ¶1). Instead, applicant argues, the memory system controller in Harari receives one set of data via the first terminals and then modifies this data into two separate sets of data, i.e. the original data and a set of parity bits (Applicant Arguments/Remarks, page 12 ¶1). In order to reach this conclusion, however, applicant must read limitations into Claim 19 not currently found.
Claim 19 describes two separate circuits, namely a memory system controller and memory interface circuitry. The memory interface circuitry is described as connected to a first set of terminals and the memory system controller connected to a second set of terminals, although the terms ‘first’ and ‘second’ only serve to differentiate the two sets of terminals from each other and do not imply an order of activation. Although the the memory interface circuitry must be connected to the first set of terminals, the memory system controller may also be connected to the first set of terminals without conflict.
This arrangement is explicitly disclosed in Harari (Central Bus 3030 connected both to the NAND controller, including ECC Correction Engine 306, and Interface Circuitry: Harari, Figure 10B). Broadest Reasonable Interpretation includes reading this connecting set of terminals between the memory interface circuitry and memory system controller as the first set of terminals.
The remainder of Claim 19 focuses entirely on the operations of the memory interface controller, which receives first and second data and eventually outputs that data to a buffer. As previously established, however, the NAND system controller receives original input data and separates it out into two parcels of data, i.e. the original data and the parity bits (Harari, col.12:40-52). These two datasets are then transmitted, via the connecting bus, to the memory interface circuitry (Harari, col.12:52-55).
Applicant argues the parity bits cannot be interpreted as the second set of data (Applicant Arguments/Remarks, page 12, ¶1). Claim 19 never defines what the second set of data consists of, however, only that it differs from the first set of data. While parity bits are inherently related to the source data, they are not the same. Therefore, this argument is unpersuasive.
In regards to the 35 U.S.C. § 103 rejection of Independent Claim 1, applicant makes a substantially similar distinction with regards to the memory interface circuitry receiving first and second data via the first set of terminals (Applicant Arguments/Remarks, page 13, ¶1). This argument may be addressed in similar fashion as above.
In regards to Claim 14, applicant argues the starting seed value of Nelson differs from the indication of the one or more memory devices described in the claim (Applicant Arguments/Remarks, page 15, ¶¶1-2). ‘An indication of a memory device’ is not a known term of art and its use in this context unusual. Applicant is entitled to be his or her own lexicographer, but the specification in this instance fails to clearly define the term. In the absence of an applicant definition, terms are given the ordinary and customary meaning. Webster’s Unabridged Dictionary of the English Language defines ‘Indication’ as “anything serving to indicate or point out, as a sign or a token.” That is, a unique identifier.
Nelson takes an initial seed value (Nelson, col.8:7-10) and from this seed value generates a pseudo-random pattern generator (Nelson, col.7:42-50). This pseudo-random number may be used in a variety of operations, but significantly including operating as a multiple input signature register (Nelson, col.3:36-37), in other words taking a seed value and using it to specifically identify a register.
In regards to the remaining claims, applicant merely argues they should be considered allowable by virtue of dependency from otherwise allowable independent claims.
Although ultimately unpersuasive, Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2019/0121756 A1 to Tsung-Chieh Yang: Disclosing a memory storage device with an interface chip configured to couple the host device to a plurality of memory chips.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824
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