DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 07/16/2024. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 14 are independent.
Continuity/ Priority Information
The present Application 18774447 filed 07/16/2024 Claims Priority from Provisional Application 63530612, filed 08/03/2023.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zainuddin et al. (Pub. No. US 20240071544) Date Filed: 2022-08-29.
Regarding independent Claims 1, 8 and 14, Zainuddin discloses a method and system for a NAND memory with different pass voltage ramp rates, comprising:
a memory device, and a processing device coupled to the memory device; [0037] FIG. 1A illustrates a storage system 100 connected to a host system 120. Storage system 100 comprises a memory controller 102, memory package 104 for storing data, and local memory (e.g., MRAM/DRAM/ReRAM) 106.
initiating a memory access operation directed to a wordline; [0113] FIG. 8, Typically, a programming signal Vpgm is applied to the control gates (via a selected word line) during a program operation as a series of programming voltage pulses, as depicted in FIG. 9.
In step 870 of FIG. 8, the programming voltage (Vpgm) is initialized to the starting magnitude (e.g., −12-16V or another suitable level) and a program counter PC maintained by state machine 362 is initialized at 1. In step 872, a program pulse of the programming signal Vpgm is applied to the selected word line (the word line selected for programming).
determining, based on an applied ramping voltage, a ramp rate of the wordline; [0035] By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.
responsive to determining that the ramp rate satisfies a defect condition, causing the memory access operation to be aborted. [0119] If number of failed memory cells is not less than the predetermined limit, then the programming process continues at step 884 and the program counter PC is checked against the program limit value (PL). Examples of program limit values include 6, 20 and 30; however, other values can be used. If the program counter PC is not less than the program limit value PL, then the program process is considered to have failed and a status of FAIL is reported in step 888.
Regarding Claims 2, 9, 15, Zainuddin discloses the defect condition is satisfied responsive to determining that the ramp rate is less than a threshold value. [0115] If, in 876, it is determined that not all of the memory cells have reached their target threshold voltages (fail), then the programming process continues to step 880.
[0116] In step 880, the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far, failed the verify process. This counting can be done by the state machine 362, the controller 102, or other logic.
Regarding Claims 3, 10, 16, Zainuddin discloses responsive to determining that the ramp rate satisfies one of the defect condition or a second defect condition, causing a block with which the wordline is associated to be retired. [0116] In step 880, the system counts the number of memory cells that have, so far, failed the verify process. [0117] In step 882, it is determined whether the count from step 880 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is a number of bits that can be corrected by error correction codes (ECC) during a read process for the page of memory cells.
Regarding Claims 4, 17, Zainuddin discloses the applied ramping voltage corresponds to a program pulse or a program verify pulse of a program operation. [0113] FIG. 8, Typically, a programming signal Vpgm is applied to the control gates (via a selected word line) during a program operation as a series of programming voltage pulses, as depicted in FIG. 9.
Regarding Claims 11, 12, Zainuddin discloses the ramping voltage corresponds to a ramp phase of an erase operation. [0102] The memory systems discussed above can be erased, programmed and read. At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate.
Regarding independent Claims 5, 18, Zainuddin discloses causing a ramping voltage to be applied to the wordline; In step 872 of FIG. 8, a program pulse of the programming signal Vpgm is applied to the selected word line (the word line selected for programming).
responsive to determining that the ramping voltage of the wordline reaches a first voltage level, enabling a counter; responsive to determining that the ramping voltage of the wordline reaches a second voltage level, disabling the counter; [0127] As discussed above, FIG. 9 depicts the programming signal Vpgm as a series of programming voltage pulses. These programming voltage pulses are one example of doses of programming applied to a plurality of non-volatile memory cells being programmed to a data state.
determining the ramp rate based on a value of the counter. [0035] The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die. FIG. 10, illustrates memory cells store one bit of data per memory cell, depicts two of the programming voltage pulses 902 and 904 of FIG. 9.
Regarding Claims 6,19, Zainuddin discloses sensing, by a first voltage detector, the ramping voltage intercepting the first voltage level. [0152] Returning to FIGS. 3A and 3B, the voltages VWLn and VWL_unsel are applied to the word lines by the array drivers 324 of the row control circuitry 320 as selected by the circuitry of the row decoder 322 and block select 326 using voltages provided from power control 364. [0153] FIG. 15 depicts an example implementation of a multi-stage charge pump that can generate the Vpass voltage level for use of a word line driver for the WL_unsel wave form of FIG. 13.
Regarding Claims 7, 13, 20, Zainuddin discloses the counter is associated with a clock to count clock cycles. [0116] In step 880, the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have, so far, failed the verify process. This counting can be done by the state machine 362, the controller 102, or other logic.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Thoppa et al. US 20240290412 [0140] To establish the operating voltage levels for the different lines, the driver circuits ramp up the voltages to corresponding levels at a ramp rate and to a value based on trim values and setting that optimized for data read operations and verify (both program and erase). The setting of these values is a tradeoff between the speed of rapid ramp rates and the accuracy and lower current consumption of slower ramp rates.
Sutardja (US 20090052256) [0053] In other features, the ramp generator comprises a counter, a digital-to-analog converter (DAC), and a clock. The counter generates the codewords. The DAC converts the codewords and generates the first and second ramp voltages. The clock increments the counter at a different rate when the ramp generator generates the second ramp voltage than when the ramp generator generates the first ramp voltage.
Li et al. (U.S. Patent No. 7,073,104) See Abstract. In a method and system for applying a testing voltage signal, a voltage source generates the testing voltage signal that ramps from an initial voltage to an intermediate voltage with a first ramping rate. In addition, the testing voltage then ramps from the intermediate voltage to an end voltage with a second ramping rate, with the first ramping rate being greater than the second ramping rate. The present invention may be applied to particular advantage when the testing voltage signal is applied on a control gate of a flash memory cell for channel erasure of the flash memory cell. In this manner, the testing voltage signal ramps to the end voltage with reduced time for minimizing testing time.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 2, 2026
Non-Final Rejection 20251216
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV