DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election without traverse of Species 1 shown in Fig. 1 in the Response to Restriction Requirements filed on 08/17/26 is acknowledged. Together with the Response, Applicant amended paragraph 0001 of the application to show earlier applications of a same family.
Applicant stated that Claims 1-4, 6-13, and 15-20 are read on Species 1.
Status of Claims
Claims 5 and 14 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-4, 6-13, and 15-20 are examined on merits herein.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 10-11, and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over some claims of U.S. Patent No. 11/462,472, as shown in a Table of Comparison below. Although the claims at issue are not identical, they are not patentably distinct from each other.
Table of Comparison
Claims of 18/774,763
Claims of
US 11,462,472
Differences between corresponding claims of 18/774,763 and US 11,462,472
1
1
18/774,763 uses words: “semiconductor device assembly” and “semiconductor device”, where US 11,462,472 uses words: “semiconductor device package assembly” and “semiconductor device package”, respectively. In addition, US 11,462,472 has an additional limitation.
2
2
18/774,763 uses words: “semiconductor device assembly” and “semiconductor device”, where US 11,462,472 uses words: “semiconductor device package assembly” and “semiconductor device package”, respectively.
3
3+4
10
13
18/774,763 uses words: “semiconductor device assembly”, “semiconductor device”, and “resin” where US 11,462,472 uses words: “semiconductor device package assembly”, “semiconductor device package”, and “resin structure”, respectively. In addition, US 11,462,472 has an additional limitation.
11
16
18/774,763 uses words: “semiconductor device assembly” and “semiconductor device”, where US 11,462,472 uses words: “semiconductor device package assembly” and “semiconductor device package”, respectively.
17
13
18/774,763 uses words: “semiconductor device assembly”, “semiconductor device”, and “thermoset material” where US 11,462,472 uses words: “semiconductor device package assembly”, “semiconductor device package”, and “resin structure”, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Farnworth et al. (US 2006/0113682).
In re Claim 1, Farnworth teaches a semiconductor device assembly, comprising (Fig. 4A; see also 2A and/or 1C for some numbers):
a base component – including die 14 (paragraph 0053) - having a front side and a back side, the base component having a first metallization structure 46, 48 (paragraphs 0060, 0070) at the front side (being a top of layer 42, as in Fig. 2A, paragraph 0068);
a semiconductor device – including die 12 (paragraph 0053) - having a first side (as a top side), a second side (as a bottom side) with a recess (filled with a portion of interconnect 26), and a second metallization structure 56 (Fig. 1E, paragraph 0061) at the first side, the second metallization structure having a contacting region 56 exposed in the recess;
discrete conductive particles – within a stack comprised elements 26 and 86 surrounded by 24 (see Fig. 1C for number 24): 26, 24, and 86 are conductive polymers created as discrete metal particles filling an epoxy resin (paragraphs 0072, 0099, 0102) - electrically coupled to one another and at least partially positioned in the recess (see paragraph 0059 for obviousness of this coupling between discreet particles), wherein
a first subset of the discrete conductive particles – within 26 - are directly coupled to the second metallization structure at the contacting region
and a second subset of the discrete conductive particles – within 24 and 86 - are directly coupled to the first metallization structure; and
a thermoset material 94 (such as an epoxy resin, paragraph 0106) - between the front side of the base component and the second side of the semiconductor device, wherein the discrete conductive particles – of at least 24 and 86 - are in the thermoset material 94: Although Farnworth does not identify epoxy as a thermoset material – the quality of epoxy of being a thermoset material is inherent: see Jiang (US 6,765,652, column 1 lines 63-64) – on this inherency.
In re Claim 2, Farnworth teaches the semiconductor device assembly of Claim 1 as cited above, wherein the semiconductor device (comprised 12) is electrically coupled to the base component (comprised 14) via the first and second metallization structures exclusive of any through-silicon vias – as explained for Claim 1.
In re Claim 3, Farnworth teaches the semiconductor device assembly of Claim 1 as cited above and wherein the semiconductor device (including 12, Fig. 4A) includes (Fig. 4A):
a passivation layer 66 (paragraph 0078) at the first side, wherein the second metallization structure 56 is in the passivation layer 66; and
a redistribution structure – starting with layer 68 (paragraph 0080), and comprising electrical connectors 28 (paragraph 0062) - on the passivation layer 66, wherein
the redistribution structure is electrically coupled to the second metallization structure 46 (as in Fig. 4A).
In re Claim 7, Farnworth teaches the semiconductor device assembly of Claim 1 as cited above and wherein (Fig. 4A) the recess is tapered from the second side to the contacting region of the second metallization structure.
In re Claim 8, Farnworth teaches the semiconductor device assembly of Claim 1 as cited above, including the semiconductor device 12 (Fig. 4A). Farnworth does not teach that the semiconductor device 12 has a thickness between the first side and the second side less than 50 microns. However, Farnworth teaches (paragraph 0118) that a similar component may have a thickness less than 50 micron (when in the range from 20 micron to 50 microns).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the semiconductor device with a thickness less than 50 micron when it is desirable to create a thin semiconductor device assembly.
Claims 4, 10-13, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Farnworth in view of Her et al. (US 2002/0094602).
In re Claim 4, Farnworth teaches the semiconductor device assembly of Claim 3 as cited above, including the redistribution structure, but does not teach that the semiconductor device includes a semiconductor component coupled with the redistribution structure through a vertical via.
Her teaches a semiconductor device (Fig. 3, paragraph 0025) comprised a semiconductor component 226 and a redistribution layer 230, wherein the semiconductor component 226 is coupled through a non-shown via (disposed in insulating layer 234). Although Her does not teach that the via is a vertical via, it is understood that the vertical via has a shortest length and using a vertical via is beneficial for a lower power dissipation on the via.
Farnworth and Her teach analogous arts directed to semiconductor devices comprised a redistribution layer, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Farnworth device in view of the Her device, since they are from the same field of endeavor, and Her created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Farnworth assembly by substituting its first non-fully disclosed semiconductor device with a semiconductor device comprised a semiconductor component (per Her) while connecting this semiconductor component to the outside lines through a created vertical via coupled to the redistribution layer (allowing a shortest way to the outside), when it is desirable using the semiconductor device having the semiconductor component and a connection to outside lines or devices.
In re Claim 10, Farnworth teaches a semiconductor device assembly, comprising (Fig. 4A, 1C):
a first semiconductor device –comprising die 12 (paragraph 0053) - having a front side and a back side, the first semiconductor device having a first metallization structure 56 (paragraph 0061) at the front side, the first metallization structure 56 being exposed from the back side via a cavity (created between sides of adjacent parts of 12);
a second semiconductor device – comprising die 14 (paragraph 0052) having a first side (as a top side) and a second side (as a bottom side), the second semiconductor device having a second metallization structure 48, 46 (paragraph 0070) at the first side;
discrete conductive particles - within a stack comprised elements 26 and 86 surrounded by 24 (see Fig. 1C for number 24): 26, 24, and 86 are conductive polymers created as discrete metal particles filling an epoxy resin (paragraphs 0072, 0099, 0102) - electrically coupled to one another and at least partially positioned in the recess (see paragraph 0059 for obviousness of this coupling between discreet particles), wherein
a first subset of the discrete conductive particles – within 26 - are directly coupled to the first metallization structure 56 at the contacting region
and a second subset of the discrete conductive particles – within 24 and 86 - are directly coupled to the second metallization structure 46, 48; and
a resin 94 (such as an epoxy resin, paragraph 0106) between the back side of the first semiconductor device and the first side of the second semiconductor device 14, wherein the discrete conductive particles – of at least 24 and 86 - are in the resin 94
Farnworth does not teach that the first semiconductor device has a first substrate at the back side and that the second semiconductor device has a second substrate at the second side.
Her teaches a semiconductor device (Fig. 3, paragraph 0025) comprised a metallization structure (as a redistribution layer 230) at a first (top) side and a substrate 222 at an opposite side.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Farnworth semiconductor device assembly by using as the first and second semiconductor devices such that have a metallization at the front or first side, respectively (as in the Farnworth device), while having substrate at the back or second side, respectively, wherein it is desirable using the first and second semiconductor devices having a substrate and a metallization structure opposite to the substrate.
In re Claim 11, Farnworth/Her teaches the semiconductor device assembly of Claim 10 as cited above, wherein the second semiconductor device 14 is electrically coupled to the first semiconductor device 12 via the first 56 and second 46, 48 metallization structures exclusive of any through-silicon vias (paragraph 0059 of Farnworth).
In re Claim 12, Farnworth/Her teaches the semiconductor device assembly of Claim 10 as cited above and wherein (Farnworth, Figs. 1C, 4A and paragraphs below) the first semiconductor device –comprising die 12 - includes:
a passivation layer 66 (paragraph 0078) at the front side, wherein the first metallization structure 56 is in the passivation layer 66; and
a redistribution structure – comprised elements 28 (paragraph 0062) on the passivation layer 66, wherein the redistribution structure is electrically coupled to the first metallization structure 56 (paragraph 0079).
In re Claim 13, Farnworth/Her teaches the semiconductor device assembly of Claim 12 as cited above, including the first semiconductor device and the redistribution layer.
Farnworth does not teach that the first semiconductor device includes a semiconductor component coupled with the redistribution structure through a vertical via.
Her teaches a semiconductor device (Fig. 3, paragraph 0025) comprised a semiconductor component 226 and a redistribution layer 230, wherein the semiconductor component 226 is coupled through a non-shown via (disposed in insulating layer 234). Although Her does not teach that the via is a vertical via, it is understood that the vertical via has a shortest length and using a vertical via is beneficial for a lower power dissipation on the via.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Farnworth/Her assembly of Claim 12 by substituting its first non-fully disclosed semiconductor device with a semiconductor device comprised a semiconductor component (per Her) while connecting this semiconductor component to the outside lines through a created vertical via coupled to the redistribution layer (allowing a shortest way to the outside), when it is desirable using the semiconductor device having the semiconductor component and a connection to outside lines or devices.
In re Claim 15, Farnworth/Her teaches the semiconductor device assembly of Claim 10 as cited above, wherein the cavity (Figs. 1C, 4A) is tapered from the back side to the front side.
In re Claim 16, Farnworth/Her teaches the semiconductor device assembly of Claim 10 as cited above, including the first semiconductor device.
Farnworth does not teach that the first semiconductor device 12 (Fig. 4A) has a thickness between the first side and the second side less than 50 microns. However, Farnworth teaches (paragraph 0118) that a similar component may have a thickness less than 50 micron (when in the range from 20 micron to 50 microns).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the first semiconductor device with a thickness less than 50 micron when it is desirable to create a thin semiconductor device assembly.
In re Claim 17, Farnworth teaches a semiconductor device assembly, comprising (Fig. 4A, 1C):
a first semiconductor device –comprising die 12 (paragraph 0053) - having a first side and a second side, the first semiconductor device having a first metallization structure 56 (paragraph 0061) at the first side, the first metallization structure being exposed from the second side via a cavity (created between sides of adjacent parts of 12);
a second semiconductor device – comprising die 14 (paragraph 0052) having a third side (as a top side) and a fourth side (as a bottom side), the second semiconductor device having a second metallization structure 48, 46 (paragraph 0070) at the third side;
discrete conductive particles - within a stack comprised elements 26 and 86 surrounded by 24 (see Fig. 1C for number 24): 26, 24, and 86 are conductive polymers created as discrete metal particles filling an epoxy resin (paragraphs 0072, 0099, 0102) - electrically coupled to one another and at least partially positioned in the recess (see paragraph 0059 for obviousness of this coupling between discreet particles), wherein
a first subset of the discrete conductive particles – within 26 - are directly coupled to the first metallization structure 56 at the contacting region
and a second subset of the discrete conductive particles – within 24 and 86 - are directly coupled to the second metallization structure 46, 48; and
a thermoset resin 94 (such as an epoxy resin, paragraph 0106) between the second side of the first semiconductor device and the third side of the second semiconductor device, wherein the discrete conductive particles – of at least 24 and 86 - are in the thermoset resin 94; although Farnworth does not state that the epoxy resin is a thermoset resin – this feature is inherent for the epoxy: see Jiang (US 6,765,652, column 1 lines 63-64) – on this inherency
Farnworth does not teach that the first semiconductor device has a first substrate at the second side and that the second semiconductor device has a second substrate at the fourth side.
Her teaches a semiconductor device (Fig. 3, paragraph 0025) comprised a metallization structure (as a redistribution layer 230) at a first (top) side and a substrate 222 at an opposite side.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Farnworth semiconductor device assembly by using as the first and second semiconductor devices such that have a metallization at the first side or the third side, respectively (as in the Farnworth device), while having substrate at the second side or the fourth side, respectively, wherein it is desirable using the first and second semiconductor devices having a substrate and a metallization structure opposite to the substrate.
In re Claim 18, Farnworth/Her teaches the semiconductor device assembly of Claim 17 as cited above, wherein the cavity (between portions of 12, Figs. 4A, 1C) is
tapered from the second side to the first side.
In re Claim 19, Farnworth/Her teaches the semiconductor device assembly of Claim 17 as cited above.
Farnworth does not teach that the first semiconductor device 12 (Fig. 4A) has a thickness between the first side and the second side less than 50 microns. However, Farnworth teaches (paragraph 0118) that a similar component may have a thickness less than 50 micron (when in the range from 20 micron to 50 microns).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the first semiconductor device with a thickness less than 50 micron when it is desirable to create a thin semiconductor device assembly.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Farnworth in view of Tsukamoto et al. (US 2003/0146990).
In re Claim 9, Farnworth teaches the semiconductor device assembly of Claim 1 as cited above, wherein the thermoset material comprises an epoxy resin, Farnworth does not teach such thermoset material as a solder anisotropic-conductivity-paste (ACP) or a solder anisotropic-conductivity-film (ACF).
Tsukamoto teaches (Figs. 3A, 3B, paragraph 0042) two structures 302 and 301 connected by an anisotropic thermoset conductive film (ACF) 303 comprised conductive particles mixed and distributed within a thermoset bonding material.
Farnworth and Tsukamoto teach analogous arts directed to a package assembly comprised a thermoset epoxy mixed with conductive particles, and one of ordinary skill in the art before filing the application would have and a reasonable expectation of success in modifying the Farnworth device in view of the Tsukamoto device, since they are from the same field of endeavor, and the Tsukamoto created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Farnworth device by substituting its thermoset epoxy, including the thermoset epoxy mixed with conductive - with an ACF of Tsukamoto, when such thermoset material is desired by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 20, Farnworth/Her teaches the semiconductor device assembly of Claim 17 as cited above, wherein the thermoset material comprises an epoxy resin. Farnworth/Her does not teach such thermoset material as a solder anisotropic-conductivity-paste (ACP) or a solder anisotropic-conductivity-film (ACF).
Tsukamoto teaches (Figs. 3A, 3B, paragraph 0042) two structures 302 and 301 connected by an anisotropic thermoset conductive film (ACF) 303 comprised conductive particles mixed and distributed within a thermoset bonding material.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Farnworth/Her device by substituting its thermoset epoxy, including the thermoset epoxy mixed with conductive - with an ACF of Tsukamoto, when such thermoset material is desired by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Farnworth in view of Thomas et al. (US 2005/0194674).
In re Claim 6, Farnworth teaches the semiconductor device assembly of Claim 3 as cited above, including the semiconductor device comprised a redistribution structure (as shown for Claim 3).
Farnworth further teaches a semiconductor device assembly comprising (Fig. 4B) a package-level substrate having a third metallization structure – the third metallization structure is pad similar to pad 56 of Fig. 4A, but disposed above the semiconductor device 14S-1 – as device 12, the third metallization structure is coupled with the second metallization structure 56 (of 14S-1) through an interconnect structure 26. However, the assembly of Fig. 4B does not have the semiconductor device (such that includes die 14S-1) comprising a redistribution structure – the only redistribution structure the assembly of Fig. 4B has – is on the top of the structure, not between adjacent semiconductor devices.
Thomas teaches a stacked semiconductor device assembly in which each die has a redistribution structure at its top (Claim 48).
Farnworth and Thomas teach analogous arts directed to a stack of semiconductor devices, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Farnworth assembly in view of the Thomas assembly, since they are from the same field of endeavor, and the Thomas assembly successfully functions.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Farnworth assembly of Claim 3 by substituting its semiconductor devices not having a redistribution structure at the top -with semiconductor devices having a redistribution structure at the top, and as such, creating the Farnworth structure of Fig. 4B with a redistribution structure on top of the semiconductor device comprised die 14S-1, wherein the manufacturer prefers having each semiconductor device in the stack of semiconductor devices – comprising a redistribution structure.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center - for more information about Patent Center and visit https://www.uspto.gov/patents/docx - for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 08/19/26
Prosecution Insights