DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 07/16/2024. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 18774799 filed 07/16/2024 Claims Priority from Provisional Application 63584765, filed 09/22/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weathers et al. (U.S. Patent No. 9,13,6011) Pub. Date: 2015-09-15.
Regarding independent Claims 1, 8 and 15, Weathers discloses a system and method for generating reliability information, such as "soft information," from a flash memory device, comprising:
a processing device coupled with a memory device;
FIG. 1 illustrates a flash storage device 100 including a data storage controller 101, a ECC module 102, a soft information module (SIM) 103 and an array of flash memory devices 104, coupled to a host 105 via a host interface 106.
performing a first data integrity scan on a block of the memory device to determine a first combined reliability statistic of memory cells in the block associated with a first program level and a second program level;
FIG. 12 depicts a process for generating reliability information corresponding to “combined reliability statistic” from a flash memory device. According to some aspects, one or more blocks of FIG. 12 may be executed by one or more components of data storage controller 101 in connection with soft information module 103. Data storage controller 101 is configured to perform read operations to read data stored in a page of memory cells of one or more flash devices 104. For the purpose of this disclosure a "page" of memory cells may refer to a page, block, sector, codeword, or other unit of data read from flash memory.
In block 1201, a plurality of memory cells are read using a first read level to obtain a plurality of program values. In some aspects, the first read level may be determined based on whether the page of memory cells being read is a LSB or MSB page. In block 1202, an error indicator is received in connection with the reading of the plurality of memory cells. For example, the plurality of program values may be sent to a decoder, which cannot decode the program values because of errors.
performing, using a predetermined read level offset corresponding to one of the first program level or the second program level, a second data integrity scan on the block of the memory device to determine a second combined reliability statistic of the memory cells in the block associated with the first program level and the second program level;
In block 1203, in response to receiving the error indicator, the plurality of memory cells are read at one or more different read levels corresponding to “predetermined read level offset” to categorize the plurality of memory cells into two or more cell program regions. Accordingly, the first read level may be based on a predetermined threshold for distinguishing between two potential programming values of a memory cell (e.g., to determine the LSB).
determining a difference between the first combined reliability statistic and the second combined reliability statistic, and responsive to the difference, performing a corrective action on the block of the memory device.
In block 1204, a confidence value corresponding to “corrective action” is assigned to each memory cell based on a corresponding cell program region for the memory cell, the confidence value being representative of a likelihood that the memory cell is programmed to a corresponding program value read at the first read level. For example, each confidence value may be a LLR value.
Regarding Claims 2, 9, 16, Weathers discloses detecting an occurrence of a data integrity check trigger event, and performing the first data integrity scan; FIG. 12, In block 1202, an error indicator “trigger event” is received in connection with the reading of the plurality of memory cells. For example, the plurality of program values may be sent to a decoder, which cannot decode the program values because of errors. The program values are forwarded to ECC module 102 for error correcting, however, but the amount of errors may be too high for ECC module 102 to correct (e.g., above a predetermined threshold).
Regarding Claims 3, 10, 17, Weathers discloses wherein the first data integrity scan is performed using default read voltages, comprises at least one of a lower-page or an extra-page read operation. FIG. 13 illustrates an example for read levels “default read voltages” and cell program regions. As binary values are read from the memory cells, one or two lookup tables is used to determine which region each value belongs. In this regard, the region discriminator receives a page bit representative of whether the page being read is a MSB bit page, and a LSB bit for a corresponding MSB page.
Regarding Claims 4,11, 18, Weathers discloses determining whether the first combined reliability statistic satisfies a scan threshold criterion, and performing the second data integrity scan. In some aspects, error signals may be based on an average LLR and/or an average sign value produced by LLR mapper 1102 satisfying a predetermined threshold. FIG. 21B, The determination of the average LLR and/or average sign value will be described further with respect to FIGS. 23 and 24. In some aspects, the error may result from a shift in the V.sub.T distributions occurring during the reading process relative to the V.sub.T distributions observed during calibration.
Regarding Claims 5, 12, 19, Weathers discloses wherein the modified first read voltage comprises a first read voltage applied during the first data integrity scan modified by the predetermined read level offset;
See SUMMARY of the invention. In one aspect, the method may include reading a plurality of memory cells at a first read level “first read voltage” to obtain a plurality of program values, receiving an error indicator in connection with the reading of the plurality of memory cells;
wherein the second read voltage comprises a same read voltage applied during the first data integrity scan. See SUMMARY of the invention. reading, in response to receiving the error indicator, the plurality of memory cells at one or more different read levels “second read voltage” to categorize the plurality of memory cells into two or more cell program regions.
Regarding Claims 6, 7, 13, 14, 20, Weathers discloses wherein the corrective action comprises folding data in the block to another block of the memory device, and marking the block for garbage collection and reprogramming data from the block to another block of the memory device. FIG. 12, In block 1202, The program values are forwarded to ECC module 102 for error correcting, however, but the amount of errors may be too high for ECC module 102 to correct (e.g., above a predetermined threshold). In this case, data controller 101 or ECC module 102 may forward the program values to soft information module 103 to generate reliability information for the program values for use in further decoding operations.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
TAO et al. (US 20190190541) [0032] To determine a probability that the memory cells were actually programmed to the observed putative program levels (i.e., read raw data), multiple read operations may be initiated as part of a multi-stage decoding operation
YANG et al. (US 20140281766) [0038] For example, based on the outcome of the probability based test 123 of FIG. 1, the lower page 224 may be read by performing a first sensing operation using a first read voltage 232, corresponding to a boundary between the erase state and state A, and performing a second sense operation using a second read voltage 234, corresponding to a boundary between state D and state E.
KARAKULAK et al. (US 20160147582) see Abstract. A table of error counts is generated based on reading wordlines of a flash memory device, the table storing an error count for each combination of wordline and respective read level voltage used to read the wordlines.
Yoon (US 9,147,483) see SUMMARY of the invention. The controller may include a microprocessor to change a first read voltage, which is used to determine whether the data stored in the memory cells is a first voltage state or a second voltage state, to a first select read voltage which is any one of n candidate voltages different from each other by a first voltage, and to change a second read voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 2, 2026
Non-Final Rejection 20251218
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV