Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 9 and 18
b. Pending: 1-25
Claims 1-2, 9-10 and 18-19 have been amended.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Specification
The new title is reviewed and accepted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18, 23-24, 1 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hossain et al. (US 20160217872).
Regarding independent claim 18, Hossain discloses a reference voltage adjustment method for a memory storage device (Fig. 9), the reference voltage adjustment method comprising:
obtaining a first signal (Fig. 9 and [0057] describes receiving an input signal at step 902) and a plurality of reference voltage levels (Fig. 9 and [0057] describes multiple adjustable comparator's reference voltages at step 904);
sensing a voltage relative relationship between the first signal and the plurality of reference voltage levels (Fig. 9 and [0057] describes a first set of result signals based on comparing the first sampled voltage with each adjustable comparator's reference voltage), wherein the voltage relative relationship is configured to identify bit data carried by the first signal (Fig. 4A and [0035] describes comparator outputs can be processed separately and the generated digital bits (i.e., the MSBs and LSBs) can be concatenated to generate the complete digital output);
detecting edge information of the first signal (Fig. 9 and [0057] describes sampling the input signal based on an edge-detection clock signal to obtain a second sampled voltage (operation 906)); wherein the edge information reflects that a voltage of the first signal changes between a first critical voltage and a second critical voltage (Figs. 2B, 2C 3A and [0033] describes that control-logic circuitry 312 can predict the voltage range of the input signal in the next clock edge of clock signal 304 (as shown in FIG. 2B), and set reference voltages 314 to cover the predicted voltage range of the input signal (as shown in FIG. 2C). Note that the reference voltages of the plurality of comparators can be spread uniformly or non-uniformly over the predicted voltage range of the future sample of the input signal. In some embodiments, the control-logic circuitry can predict the voltage range of the future sample of the input signal based on result signals 310 outputted by the plurality of comparators. Specifically, the control-logic circuitry can predict the voltage range of the future sample of the input signal based on result signals 310 outputted by fixed comparators, adjustable comparators, or both fixed and adjustable comparators. When there is a range for signal voltage that means it varies within two maximum and minimum voltage values); and
adjusting at least one of the plurality of reference voltage levels according to the edge information (Fig. 9 and [0057] describes multiple adjustable comparators in the second set of adjustable comparators has a respective reference voltage that is adjustable (operation 908). The process can then predict a first voltage range of a future sample of the input signal based on the first result signals, and predict a second voltage range of a future sample of the input signal based on the second result signals (operation 910). Next, the process can set reference voltages of the first set of adjustable comparators based on the predicted second voltage range, and set reference voltages of the second set of adjustable comparators based on the predicted first voltage range (operation 912)).
Regarding claim 23, Hossain discloses all the elements of claim 18 as above and further a bit depth of the bit data is at least 2 ([0050] describes that it is possible to achieve 4 to 5 bit resolution using 4 to 6 comparators only).
Regarding claim 24, Hossain discloses all the elements of claim 18 as above and further the at least one of the plurality of reference voltage levels is adjusted in real time (Fig. 4B and [0036] describes that reference voltages for adjustable comparators can change over time) after a connection between the memory storage device and a host system is established (Fig. 10 shows transmitter 1002 (which acts as host) and Receiver 1004).
Regarding independent claim 1, Hossain discloses a signal receiving circuit (Figs. 9-10 shows receiver 1004), comprising:
a multi-stage sensing circuit (Fig. 7A and [0050] describes a plurality of comparators (708 and 758) to output result signals based on comparing the sampled edge voltage with each adjustable comparator's reference voltage);
an edge detecting circuit (Fig. 7A shows edge-detection clock signal 754 being output from block 720); and a control circuit coupled to the multi-stage sensing circuit and the edge detecting circuit (Fig. 7A shows control-logic circuitry 712 being connected to plurality of comparators and block 720),
the remaining part of device claim 1 recites same claim limitations as independent method claim 18 and henceforth rejected the same way.
Regarding claim 6, Hossain discloses all the elements of claim 1 as above and further a bit depth of the bit data is at least 2 ([0050] describes that it is possible to achieve 4 to 5 bit resolution using 4 to 6 comparators only).
Regarding claim 7, Hossain discloses all the elements of claim 1 as above and further the at least one of the plurality of reference voltage levels is adjusted in real time (Fig. 4B and [0036] describes that reference voltages for adjustable comparators can change over time) after a connection between the signal receiving circuit and a host system is established (Fig. 10 shows transmitter 1002 (which acts as host) and Receiver 1004).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. (US 20160217872) in view of Wyland (US 20160363654).
Regarding independent claim 9, Wyland discloses a memory storage device (Fig. 1), comprising:
Hossain discloses a connection interface unit configured to be coupled to a host system (Fig. 10 shows Transmitter 1002 (host) connected to Receiver 1004);
Wyland teaches a rewritable non-volatile memory module (Fig. 1 shows memory 107); and
a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module (Fig. 1 of Wyland shows Controller 108 connected to Memory 107),
the remaining part of device claim 9 recites same claim limitations as independent method claim 18 and henceforth rejected the same way with Hossain.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Wyland to Hossain such that accurate time-of-flight (TOF) measurements can be made as taught by Wyland (Abstract).
Regarding claim 14, Hossain and Wyland together disclose all the elements of claim 9 as above and through Hossain further a bit depth of the bit data is at least 2 ([0050] describes that it is possible to achieve 4 to 5 bit resolution using 4 to 6 comparators only).
Regarding claim 15, Hossain and Wyland together disclose all the elements of claim 9 as above and through Hossain further the least one of the plurality of reference voltage levels is adjusted in real time (Fig. 4B and [0036] describes that reference voltages for adjustable comparators can change over time) after a connection between the connection interface unit and the host system is established (Fig. 10 shows transmitter 1002 (which acts as host) and Receiver 1004).
Claim 16 recites partial claim limitations from claim 1 and henceforth rejected the same way.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Hossain et al. (US 20160217872) in view of Wang (US 20180287831).
Regarding claim 25, Hossain discloses all the elements of claim 18 as above and further obtaining an input signal; performing a first compensation on the input signal to generate the first signal; generating a second signal according to the first signal (Fig. 9 shows generating first sampled voltage at step 902); performing a second compensation on the second signal to generate a third signal (Fig. 9 shows generating a first set of results signals at step 904); and performing at least one of frequency tracking and phase tracking on the third signal to generate a fourth signal (Fig. 9 shows generating a second set of results signals at step 908); and the step of obtaining the edge information of the first signal (step 906 of Fig. 9) comprising: obtaining the edge information of the first signal according to the fourth signal (step 910 of Fig. 9 shows the dependency).
Hossain doesn’t disclose obtaining an input signal; performing a first compensation on the input signal to generate the first signal;
However, Wang teaches obtaining an input signal; performing a first compensation on the input signal to generate the first signal ([0035] describes offsetting the incoming signal);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Wang to Hossain such that DC offset may be compensated to ensure detectable data transitions for reference level adaptation as taught by Wang (Abstract).
Allowable Subject Matter
Claims 2-5, 8, 10-13, 17 and 19-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on 5/28/2026 have been fully considered but they are not persuasive.
Primary reference Hossain et al. (US 20160217872) in Figs. 2B, 2C 3A and [0033] describes that control-logic circuitry 312 can predict the voltage range of the input signal in the next clock edge of clock signal 304 (as shown in FIG. 2B), and set reference voltages 314 to cover the predicted voltage range of the input signal (as shown in FIG. 2C). Note that the reference voltages of the plurality of comparators can be spread uniformly or non-uniformly over the predicted voltage range of the future sample of the input signal. In some embodiments, the control-logic circuitry can predict the voltage range of the future sample of the input signal based on result signals 310 outputted by the plurality of comparators. Specifically, the control-logic circuitry can predict the voltage range of the future sample of the input signal based on result signals 310 outputted by fixed comparators, adjustable comparators, or both fixed and adjustable comparators. When there is a range for signal voltage that means it varies within two maximum and minimum voltage values.
Rejections are maintained at-least for above mentioned reasons. Details will be found under “Claim Rejections”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 6/24/2026
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