DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al. (US7659126), hereinafter referred to as ‘Smith’, Song et al. (US10432183), hereinafter referred to as ‘Song’, Peng et al. (US20150323588), hereinafter referred to as ‘Peng’, and Sumita et al. (US20110090015), hereinafter referred to as ‘Sumita’.
Regarding Claim 1, Smith discloses a device for measuring a frequency response of a wafer, comprising: a first oscillator, configured to provide a first signal having a first frequency (FIG. 3A shows a top plan view schematic of a meander-type test structure 302 coupled to a ring-type oscillator circuit 300. The meander test structure 302 may be formed from a metal layer (e.g., metal 1) that is to be characterized. The frequency and bandwidth of a signal from the oscillator 300 and test structure 302 gives an indication of the performance of the transistors that make up the oscillator and the metal used in the interconnects, Col. 5, Lines 52-59); and a first circuit on the wafer and having a first number of parallelly connected ring oscillators (Embodiments of the present invention provide a simple and relatively inexpensive way to power up test oscillator circuits in parallel during semiconductor fabrication, Col. 7, Lines 36-38); wherein a first portion of each ring oscillator of the first circuit (FIG. 6 schematically illustrates one possible scheme for implementing such cross-chip performance variation. Different ring oscillators 602A, 602B are placed at different locations on a chip 604. The oscillators may be fabricated, e.g., as described above with respect to FIGS. 2A-2B. Although two ring oscillators are shown for the sake of clarity, it is noted that any number of oscillators may be used, Col. 6, Lines 46-53).
However, Smith does not explicitly disclose a clock generator, configured to receive the first signal and generate a first clock signal and a second clock signal from the first signal, wherein the first clock signal and the second clock signal have having the first frequency and different duty cycles; and a first circuit on the wafer and having a first number of parallelly connected ring oscillators; and a first driver, coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit, wherein a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.
Nevertheless, Song discloses a clock generator, configured to receive the first signal and generate a first clock signal and a second clock signal from the first signal (According to some embodiments of the inventive concept, there is provided a clock generation circuit including; a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal, Col. 1, Lines 41-54), wherein the first clock signal and the second clock signal have having the first frequency and different duty cycles (…the first and second waveform signals PH0 and PH1 has a period that is about three times (3X) the period of the input clock signal CLKIN, each one of the first and second waveform signals PH0 and PH1 has a different duty ratio, Col. 7, Lines 5-9); and a first driver, coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit (According to some embodiments of the inventive concept, there is provided a clock generation circuit including; a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal, Col. 1, Lines 41-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith with the teachings of Song to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
However, the Smith and Song does not explicitly disclose a first driver, coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit and wherein a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.
Nevertheless, Peng discloses a first driver (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith and Song with the teachings of Peng to drive the circuit and establish the frequency for the circuit and improve the accuracy of the clock generator.
However, Smith, Song, and Peng wherein a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit.
Nevertheless, Sumita discloses a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit (The first ring oscillator includes a switch circuit configured to switch between a first connection state in which ring connection of the first ring oscillator is disconnected to connect a predetermined node of the second ring oscillator to a predetermined node of the first ring oscillator, and a second connection state in which connection between the first ring oscillator and the second ring oscillator is disconnected to connect the first ring oscillator in a ring [0011]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng with the teachings of Sumita to determine difference between signal delay of the 7-stage inverter chain (see FIG. 2) in the ring oscillator 11 including the tri-state inverter 115 and six of the inverters 111 between the node 116 and the node 114 (Sumita [0041]).
Regarding Claim 2, Smith, Song, Peng, and Sumita disclose the claimed invention discussed in claim 1.
Smith discloses a second circuit on the wafer and having the first number of parallelly connected oscillators (FIGS. 2A-2B depict a ring type oscillator circuit 200 according to an embedment of the invention. The oscillator circuit 200 may be one of several such circuits built into a semiconductor wafer, Col. 3, Lines 53-56; Embodiments of the present invention provide a simple and relatively inexpensive way to power up test oscillator circuits in parallel during semiconductor fabrication, Col. 7, Lines 36-38).
Regarding Claim 3, Smith, Song, Peng, and Sumita disclose the claimed invention discussed in claim 2.
Smith discloses a third circuit on the wafer and having the first number of parallelly connected second oscillators (Embodiments of the present invention provide a simple and relatively inexpensive way to power up test oscillator circuits in parallel during semiconductor fabrication, Col. 7, Lines 36-38; ).
However, Smith and Sumita do not explicitly disclose the first driver coupled to the first circuit and the second circuit.
Nevertheless, Song discloses the first driver coupled to the first circuit and the second circuit (…Referring to FIGS. 1 and 3, the clock generation circuit 100B further includes a waveform generator 150, as compared to the clock generation circuit 100A illustrated in FIG. 1, Col. 5, Lines 12-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith and Song with the teachings of Sumita to ensure the signal is strength for circuit components and minimize the risk of damage or interference to circuit components.
However, Smith, Song, and Sumita do not explicitly disclose the first driver coupled to the first circuit and the second circuit.
Nevertheless, Peng discloses the first driver (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, and Peng with the teachings of Sumita to drive the circuit and establish the frequency for the circuit and improve the accuracy of the clock generator.
Regarding Claim 4, Smith, Song, Peng, and Sumita disclose the claimed invention discussed in claim 3.
Smith discloses the third circuit (as discussed above).
However, Smith discloses a second driver coupled with the third circuit, wherein the second driver is configured to receive the first clock signal and the second clock signal.
Nevertheless, Song a driver coupled with the third circuit, wherein the driver is configured to receive the first clock signal and the second clock signal (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith and Song with the teachings of Sumita to ensure the signal is strength for circuit components and minimize the risk of damage or interference to circuit components.
However, Smith, Song, and Sumita do not explicitly disclose a driver coupled with the third circuit, wherein the driver is configured to receive the first clock signal and the second clock signal.
Nevertheless, Peng discloses a driver (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, and Peng with the teachings of Sumita to drive the circuit and establish the frequency for the circuit and improve the accuracy of the clock generator.
Regarding Claim 5, Smith, Song, Peng, and Sumita disclose the claimed invention discussed in claim 3.
However, Smith, Peng, and Sumita do not explicitly disclose a rising edge of the first clock signal is not aligned with a rising edge of the second clock signal.
Nevertheless, Song discloses a rising edge of the first clock signal is not aligned with a rising edge of the second clock signal (The output clock signal CLKOUT has a waveform in which skew of a rising edge is eliminated or reduced as compared to the first and second waveform signals PH0 and PH1, Col. 6, Lines 26-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, and Peng with the teachings of Sumita to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
Regarding Claim 6, Smith, Song, Peng, and Sumita disclose the claimed invention discussed in claim 3.
However, Smith, Peng, and Sumita does not explicitly disclose a falling edge of the first clock signal is not aligned with a falling edge of the second clock signal.
Nevertheless, Song discloses a falling edge of the first clock signal is not aligned with a falling edge of the second clock signal (In other words, the clock generation circuit 100A may result in a single-edge deskew function by which skew of either the rising edge or the falling edge of the output clock signal CLKOUT is eliminated or significantly reduced, Col. 5, Lines 1-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, and Peng with the teachings of Sumita to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
Regarding Claim 11, Smith, Song, Peng, and Sumita disclose the claimed invention discussed in claim 1.
However, Smith does not explicitly disclose a first duty cycle of the first clock signal is larger than a second duty cycle of the second clock signal.
Nevertheless, Song discloses the clock signal (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith and Song with the teachings of Sumita to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
However, Smith, Song, and Peng do not explicitly disclose a first duty cycle of the first clock signal is larger than a second duty cycle of the second clock signal.
Nevertheless, Sumita discloses a duty cycle of the clock signal (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, and Peng with the teachings of Sumita to ensure that the clock signal alternates between two voltage levels while reducing the phase noise and jitter.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Smith, Song, Peng, and Sumita, and further in view of Jung et al. (US20180224498) hereinafter referred to as ‘Jung’.
Regarding Claim 7, Smith, Song, Peng, and Sumita disclose the claimed invention discussed in claim 2.
Smith discloses the first portion of each ring oscillator of the first circuit (as discussed above).
However, Smith, Song, Peng, and Sumita does not disclose the first portion of each ring oscillator of the first circuit is formed during a front-end-of-line (FEOL) of the wafer, and the second portion of each ring oscillator of the first circuit is formed during a back-end-of-line (BEOL) of the wafer.
Nevertheless, Jung discloses the first portion of each ring oscillator of the first circuit is formed during a front-end-of-line (FEOL) of the wafer, and the second portion of each ring oscillator of the first circuit is formed during a back-end-of-line (BEOL) of the wafer (The first functional block 110 may include a plurality of ring oscillators RO in addition to circuit components constituting the first functional block 110. In some embodiments, the semiconductor device 100 may include first ring oscillators FEOL_RO and second ring oscillators BEOL_RO having different configurations. More specifically, the first ring oscillators FEOL_RO may be front end of line (FEOL) ring oscillators, and the second ring oscillators BEOL_RO may be back end of line (BEOL) ring oscillators. The first ring oscillator FEOL_RO may include a plurality of first ring oscillators FRO1 through FROn. [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita with the teachings of Jung to isolate the first and second portion for testing and to compare/analyze the electrical measurements of the first and second portion to identify characteristics of the wafer.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Smith, Song, Peng, Sumita, and Jung and further in view of Yuan et al. (US20050149777) hereinafter referred to as ‘Yuan’.
Regarding Claim 8, Smith, Song, Sumita, and Jung discloses the claimed invention discussed in claim 7.
Smith discloses the first portion of each ring oscillator of the circuit (as discussed above).
However, Smith, Song, Peng, Sumita, and Jung does not explicitly disclose the first portion of each ring oscillator of the first circuit is disconnected from the second portion of each ring oscillator of the first circuit.
Nevertheless, Yuan discloses the first portion of each ring oscillator of the first circuit is disconnected from the second portion of each ring oscillator of the first circuit (Thus, while a rough idea of the relative delay contributions from FEOL and BEOL components can be determined by simply subtracting the output delay of an unloaded test circuit from the output delay of a loaded test circuit, a more accurate determination of the FEOL/BEOL delay contributions requires a more sophisticated approach [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, Sumita, and Jung with the teachings of Yuan to have a more accurate determination of the FEOL/BEOL delay contributions of the first and second portion (Yuan [0042]).
Regarding Claim 9, Smith, Song, Peng, Sumita, and Jung discloses the claimed invention discussed in claim 8.
Smith discloses the portion of each ring oscillator of the circuit (as discussed above).
However, Smith, Song, Peng, Sumita, and Jung does not explicitly disclose the first portion of each ring oscillator of the first circuit is formed before a first metal layer of the wafer, and the second portion of each ring oscillator of the first circuit.
Nevertheless, Yuan discloses the first portion of each ring oscillator of the first circuit is formed before a first metal layer of the wafer, and the second portion of each ring oscillator of the first circuit (BEOL components are defined by the particular process layer in which they are formed. For example, the interconnects formed in the metal-1 layer (M1 interconnects) represent a first type of BEOL component, while the interconnects formed in the metal-2 layer (M2 interconnects) represent a second type of BEOL component [0037]; while the output delay from an unloaded test circuit will be primarily driven by the (FEOL) transistors making up the ring oscillator, the (BEOL) interconnects that connect all those transistors will also have some effect [0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Sumita, and Jung with the teachings of Yuan to have a more accurate determination of the FEOL/BEOL delay contributions of the first and second portion (Yuan [0042]).
Regarding Claim 10, Smith, Song, Peng, Sumita, and Jung disclose the claimed invention discussed in claim 9.
Smith discloses each ring oscillator of the circuit (as discussed above).
However, Smith, Song, Peng, Sumita, and Jung does not explicitly disclose a third portion of each ring oscillator of the second circuit is formed before a second metal layer of the wafer, and a fourth portion of each ring oscillator of the second circuit is formed after the second metal layer of the wafer.
Nevertheless, Yuan discloses a portion of each ring oscillator of the circuit is formed before a metal layer of the wafer, and a portion of each ring oscillator of the circuit is formed after the metal layer of the wafer (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, Sumita, and Jung with the teachings of Yuan to reduce noise and interference while maintaining a reliable path for signals to travel and improve the oscillator’s stability and performance.
Claims 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Smith, Song, Peng, Sumita in further view of Yuan.
Regarding Claim 12, Smith discloses a device for measuring a frequency response of a wafer, comprising: a first oscillator, configured to provide a first signal having a first frequency (FIG. 3A shows a top plan view schematic of a meander-type test structure 302 coupled to a ring-type oscillator circuit 300. The meander test structure 302 may be formed from a metal layer (e.g., metal 1) that is to be characterized. The frequency and bandwidth of a signal from the oscillator 300 and test structure 302 gives an indication of the performance of the transistors that make up the oscillator and the metal used in the interconnects, Col. 5, Lines 52-59); and a first circuit on the wafer and having a first number of parallelly connected ring oscillators (Embodiments of the present invention provide a simple and relatively inexpensive way to power up test oscillator circuits in parallel during semiconductor fabrication, Col. 7, Lines 36-38); wherein a first portion of each ring oscillator of the first circuit (FIG. 6 schematically illustrates one possible scheme for implementing such cross-chip performance variation. Different ring oscillators 602A, 602B are placed at different locations on a chip 604. The oscillators may be fabricated, e.g., as described above with respect to FIGS. 2A-2B. Although two ring oscillators are shown for the sake of clarity, it is noted that any number of oscillators may be used, Col. 6, Lines 46-53).
However, Smith does not explicitly disclose clock generator, configured to receive the first signal and generate a first clock signal and a second clock signal from the first signal, wherein the first clock signal and the second clock signal have the first frequency and different duty cycles; and a first circuit on the wafer and having a first number of parallelly connected ring oscillators; and a first driver, coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit, wherein a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit wherein each ring oscillator of the first circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer, wherein the first portion of each ring oscillator of the first circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each ring oscillator of the first circuit formed during the back-end-of-line of the wafer.
Nevertheless, Song discloses a clock generator, configured to receive the first signal and generate a first clock signal and a second clock signal from the first signal (According to some embodiments of the inventive concept, there is provided a clock generation circuit including; a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal, Col. 1, Lines 41-54), wherein the first clock signal and the second clock signal have having the first frequency and different duty cycles (…the first and second waveform signals PH0 and PH1 has a period that is about three times (3X) the period of the input clock signal CLKIN, each one of the first and second waveform signals PH0 and PH1 has a different duty ratio, Col. 7, Lines 5-9); and a first driver, coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit (According to some embodiments of the inventive concept, there is provided a clock generation circuit including; a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal, Col. 1, Lines 41-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith with the teachings of Song to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
However, the Smith and Song do not explicitly disclose a first driver, coupled to the first circuit and the clock generator, and configured to receive the first clock signal and the second clock signal, and drive the first circuit, wherein a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit and wherein each ring oscillator of the first circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer, wherein the first portion of each ring oscillator of the first circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each ring oscillator of the first circuit formed during the back-end-of-line of the wafer.
Nevertheless, Peng discloses a first driver (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith and Song with the teachings of Peng to drive the circuit and establish the frequency for the circuit and improve the accuracy of the clock generator.
However, Smith, Song, and Peng do not explicitly disclose wherein a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit and wherein each ring oscillator of the first circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer, wherein the first portion of each ring oscillator of the first circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each ring oscillator of the first circuit formed during the back-end-of-line of the wafer.
Nevertheless, Sumita discloses a first portion of each ring oscillator of the first circuit is electrically disconnected from a second portion of each ring oscillator of the first circuit (The first ring oscillator includes a switch circuit configured to switch between a first connection state in which ring connection of the first ring oscillator is disconnected to connect a predetermined node of the second ring oscillator to a predetermined node of the first ring oscillator, and a second connection state in which connection between the first ring oscillator and the second ring oscillator is disconnected to connect the first ring oscillator in a ring [0011]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, and Peng with the teachings of Sumita to determine difference between signal delay of the 7-stage inverter chain (see FIG. 2) in the ring oscillator 11 including the tri-state inverter 115 and six of the inverters 111 between the node 116 and the node 114 (Sumita [0041]).
However, Smith, Song, Peng, and Sumita do not explicitly disclose and wherein each ring oscillator of the first circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer, wherein the first portion of each ring oscillator of the first circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each ring oscillator of the first circuit formed during the back-end-of-line of the wafer.
Nevertheless, Yuan disclosed each ring oscillator of the first circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer, wherein the first portion of each ring oscillator of the first circuit formed during the front-end-of-line of the wafer is electrically disconnected from the second portion of each ring oscillator of the first circuit formed during the back-end-of-line of the wafer (Thus, while a rough idea of the relative delay contributions from FEOL and BEOL components can be determined by simply subtracting the output delay of an unloaded test circuit from the output delay of a loaded test circuit, a more accurate determination of the FEOL/BEOL delay contributions requires a more sophisticated approach [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita with the teachings of Yuan to have a more accurate determination of the FEOL/BEOL delay contributions of the first and second portion (Yuan [0042]).
Regarding Claim 13, Smith, Song, Peng, Sumita, and Yuan disclose the claimed invention discussed in claim 12.
However, Smith, Peng, Sumita, and Yuan does not explicitly disclose a rising edge of the first clock signal is not aligned with a rising edge of the second clock signal, and a falling edge of the first clock signal is not aligned with a falling edge of the second clock signal.
Nevertheless, Song discloses a rising edge of the first clock signal is not aligned with a rising edge of the second clock signal, and a falling edge of the first clock signal is not aligned with a falling edge of the second clock signal (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita with the teachings of Yuan to establish and maintain a stable and consistent clock signal to improve manage the operation of the circuit components.
Regarding Claim 14, Smith, Song, Peng, Sumita, and Yuan discloses the claimed invention discussed in claim 12.
However, the Smith, Song, Peng, and Sumita, do not explicitly disclose the first portion of each ring oscillator of the first circuit is formed before a first metal layer of the wafer, and the second portion of each ring oscillator of the first circuit is formed after the first metal layer of the wafer.
Nevertheless, Yuan discloses the first portion of each ring oscillator of the first circuit is formed before a first metal layer of the wafer, and the second portion of each ring oscillator of the first circuit is formed after the first metal layer of the wafer (BEOL components are defined by the particular process layer in which they are formed. For example, the interconnects formed in the metal-1 layer (M1 interconnects) represent a first type of BEOL component, while the interconnects formed in the metal-2 layer (M2 interconnects) represent a second type of BEOL component [0037]; while the output delay from an unloaded test circuit will be primarily driven by the (FEOL) transistors making up the ring oscillator, the (BEOL) interconnects that connect all those transistors will also have some effect [0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita, with the teachings of Yuan to have a more accurate determination of the FEOL/BEOL delay contributions of the first and second portion (Yuan [0042]).
Regarding Claim 15, Smith, Song, Peng, Sumita, and Yuan discloses the claimed invention discussed in claim 12.
Smith discloses a second circuit on the wafer and having the first number of parallelly connected ring oscillators; and a third circuit on the wafer and having the first number of parallelly connected ring oscillators (FIGS. 2A-2B depict a ring type oscillator circuit 200 according to an embedment of the invention. The oscillator circuit 200 may be one of several such circuits built into a semiconductor wafer, Col. 3, Lines 53-56; Embodiments of the present invention provide a simple and relatively inexpensive way to power up test oscillator circuits in parallel during semiconductor fabrication, Col. 7, Lines 36-38).
However, Smith, Song, and Sumita, and Yuan does not explicitly disclose the first driver is coupled to the first circuit and the second circuit.
Nevertheless, Peng discloses the first driver is coupled to the first circuit and the second circuit (The voltage level may be indicated in a second signal 295. The first circuit 221 may comprise a first clock generator 222, a first oscillator 226, a clock divider 232, a level shifter 234, a periodic waveform generator 236, a mixer 244, an encoder circuit 243, a driver 245 and an emitter 242 for transmitting the first signal 291 and the second signal 295 as feedbacks to the second circuit 251 [0079]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita, with the teachings of Yuan to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
Regarding Claim 16, Smith, Song, Peng, Sumita, and Yuan discloses the claimed invention discussed in claim 15.
Smith discloses the third circuit (as discussed above).
However, Smith, Song, Sumita, and Yuan discloses a second driver coupled with the third circuit, wherein the second driver is configured to receive the first clock signal and the second clock signal.
Nevertheless, Peng a driver coupled with the third circuit, wherein the second driver is configured to receive the first clock signal and the second clock signal (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita, with the teachings of Yuan to ensure the signal is strength for circuit components and minimize the risk of damage or interference to circuit components.
Regarding Claim 17, Smith, Song, Peng, Sumita, and Yuan discloses the claimed invention discussed in claim 16.
Smith discloses each ring oscillator of the circuit (as discussed above).
However, Smith, Song, Peng, and Sumita does not explicitly disclose a third portion of each ring oscillator of the second circuit is formed before a second metal layer of the wafer, and a fourth portion of each ring oscillator of the second circuit is formed after the second metal layer of the wafer.
Nevertheless, Yuan discloses a portion of each ring oscillator of the circuit is formed before a metal layer of the wafer, and a portion of each ring oscillator of the circuit is formed after the metal layer of the wafer (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita, with the teachings of Yuan to reduce noise and interference while maintaining a reliable path for signals to travel and improve the oscillator’s stability and performance.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Smith, Song, Peng, Sumita, and Yuan, and further in view of Bell at el. (US20180294801), hereinafter referred to as ‘Bell’.
Regarding Claim 18, Smith discloses a device for measuring a frequency response of a wafer, comprising: (FIG. 3A shows a top plan view schematic of a meander-type test structure 302 coupled to a ring-type oscillator circuit 300. The meander test structure 302 may be formed from a metal layer (e.g., metal 1) that is to be characterized. The frequency and bandwidth of a signal from the oscillator 300 and test structure 302 gives an indication of the performance of the transistors that make up the oscillator and the metal used in the interconnects, Col. 5, Lines 52-59); and a first circuit on the wafer and having a first number of parallelly connected ring oscillators (Embodiments of the present invention provide a simple and relatively inexpensive way to power up test oscillator circuits in parallel during semiconductor fabrication, Col. 7, Lines 36-38); wherein a first portion of each ring oscillator of the first circuit (FIG. 6 schematically illustrates one possible scheme for implementing such cross-chip performance variation. Different ring oscillators 602A, 602B are placed at different locations on a chip 604. The oscillators may be fabricated, e.g., as described above with respect to FIGS. 2A-2B. Although two ring oscillators are shown for the sake of clarity, it is noted that any number of oscillators may be used, Col. 6, Lines 46-53), wherein each ring oscillator of the first circuit (as discussed above), and wherein the first portion of each ring oscillator of the first circuit (as discussed above).
However, Smith does not explicitly disclose a clock generator, configured to generate, based on a clock signal, two non-overlapping clock signals having a first frequency and different duty cycles; a first circuit on the wafer and having a first number of parallelly connected ring oscillators, each ring oscillator being substantially identical to a first ring oscillator of the clock generator; and a first driver, coupled to the first circuit and the clock generator, and configured to receive the two non-overlapping clock signals, and drive the first circuit, wherein a first portion of each ring oscillator of the first circuit formed during a front-end-of-line of the wafer is electrically disconnected from a second portion of each ring oscillator of the first circuit formed during a back-end-of-line of the wafer.
Nevertheless, Song discloses a clock generator, configured to generate, based on a clock signal, two non-overlapping clock signals having a first frequency and different duty cycles (According to some embodiments of the inventive concept, there is provided a clock generation circuit including; a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal, Col. 1, Lines 41-54; …the first and second waveform signals PH0 and PH1 has a period that is about three times (3X) the period of the input clock signal CLKIN, each one of the first and second waveform signals PH0 and PH1 has a different duty ratio, Col. 7, Lines 5-9); a first driver, coupled to the first circuit and the clock generator, and configured to receive the two non-overlapping clock signals (According to some embodiments of the inventive concept, there is provided a clock generation circuit including; a clock gating circuit configured to receive a first waveform signal in response to an input clock signal and generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal, Col. 1, Lines 41-54).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith with the teachings of Song to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
However, Smith and Song do not explicitly disclose a clock generator, configured to generate, based on a clock signal, two non-overlapping clock signals having a first frequency and different duty cycles; a first circuit on the wafer and having a first number of parallelly connected ring oscillators, each ring oscillator being substantially identical to a first ring oscillator of the clock generator; and a first driver, coupled to the first circuit and the clock generator, and configured to receive the two non-overlapping clock signals, and drive the first circuit, wherein a first portion of each ring oscillator of the first circuit formed during a front-end-of-line of the wafer is electrically disconnected from a second portion of each ring oscillator of the first circuit formed during a back-end-of-line of the wafer.
Nevertheless, Peng discloses a first driver (The first semiconductor die 120 may comprise a first clock generator 122. The first clock generator 122 may be provided within the first semiconductor die 120 to generate a first clock signal 124 having a first frequency f1 [0026]; The voltage level may be indicated in a second signal 295. The first circuit 221 may comprise a first clock generator 222, a first oscillator 226, a clock divider 232, a level shifter 234, a periodic waveform generator 236, a mixer 244, an encoder circuit 243, a driver 245 and an emitter 242 for transmitting the first signal 291 and the second signal 295 as feedbacks to the second circuit 251 [0079]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith and Song with the teachings of Peng to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
However, Smith, Song, and Peng does not explicitly disclose a clock generator, configured to generate, based on a clock signal, two non-overlapping clock signals having a first frequency and different duty cycles; and a first driver, coupled to the first circuit and the clock generator, and configured to receive the two non-overlapping clock signals, and drive the first circuit, wherein a first portion of each ring oscillator of the first circuit formed during a front-end-of-line of the wafer is electrically disconnected from a second portion of each ring oscillator of the first circuit formed during a back-end-of-line of the wafer.
Nevertheless, Sumita discloses a first portion of each ring oscillator of the first circuit formed during a front-end-of-line of the wafer is electrically disconnected from a second portion of each ring oscillator of the first circuit (The first ring oscillator includes a switch circuit configured to switch between a first connection state in which ring connection of the first ring oscillator is disconnected to connect a predetermined node of the second ring oscillator to a predetermined node of the first ring oscillator, and a second connection state in which connection between the first ring oscillator and the second ring oscillator is disconnected to connect the first ring oscillator in a ring [0011).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, and Peng with the teachings of Sumita to cause the ring oscillators to oscillate in a state where coupling of the output phases is weakened between different ring oscillators.
However, Smith, Song, Peng, and Sumita do not explicitly disclose a clock generator, configured to generate, based on a clock signal, two non-overlapping clock signals having a first frequency and different duty cycles; and a first driver, coupled to the first circuit and the clock generator, and configured to receive the two non-overlapping clock signals, and drive the first circuit, wherein a first portion of each ring oscillator of the first circuit formed during a front-end-of-line of the wafer is electrically disconnected from a second portion of each ring oscillator of the first circuit formed during a back-end-of-line of the wafer.
Nevertheless, Yuan discloses each ring oscillator of the first circuit includes a first portion formed during a front-end-of-line of the wafer and a second portion formed during a back-end-of-line of the wafer (Thus, while a rough idea of the relative delay contributions from FEOL and BEOL components can be determined by simply subtracting the output delay of an unloaded test circuit from the output delay of a loaded test circuit, a more accurate determination of the FEOL/BEOL delay contributions requires a more sophisticated approach [0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, and Sumita with the teachings of Yuan to have a more accurate determination of the FEOL/BEOL delay contributions of the first and second portion (Yuan [0042]).
However, Smith, Song, Peng, Sumita, and Yuan does not explicitly disclose a clock generator, configured to generate, based on a clock signal, two non-overlapping clock signals having a first frequency and different duty cycles; and a first driver, coupled to the first circuit and the clock generator, and configured to receive the two non-overlapping clock signals, and drive the first circuit.
Nevertheless, Bell discloses two non-overlapping clock signals (Since clock generator 200 is not dependent on the stages to oscillate, the number of stages is not required to be an odd number. The signals at the tap points could still be used to generate non-overlapping clocks and combinational logic can be used to generate clocks of various periods and phases (in a manner such as described with respect to FIGS. 1 and 3). Similar to clock generator 100, the amount of delay provided by each stage may or may not be the same throughout the ring oscillator, depending on the implementation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, Sumita, and Yuan with the teachings of Bell to generate clocks of various periods and phases establish and improve/ manage the operation of the circuit components.
Regarding Claim 19 Smith, Song, Peng, Sumita, Yuan, and Bell discloses the claimed invention discussed in claim 18.
Smith discloses a second circuit on the wafer and having the first number of parallelly connected ring oscillators; and a third circuit on the wafer and having the first number of parallelly connected ring oscillators (FIGS. 2A-2B depict a ring type oscillator circuit 200 according to an embedment of the invention. The oscillator circuit 200 may be one of several such circuits built into a semiconductor wafer, Col. 3, Lines 53-56; Embodiments of the present invention provide a simple and relatively inexpensive way to power up test oscillator circuits in parallel during semiconductor fabrication, Col. 7, Lines 36-38).
However, Smith, Song, Sumita, Yuan, and Bell does not explicitly disclose the first driver is coupled to the first circuit and the second circuit.
Nevertheless, Peng discloses the first driver is coupled to the first circuit and the second circuit (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, Sumita, and Yuan with the teachings of Bell to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
Regarding Claim 20, Smith, Song, Peng, Sumita, Yuan, and Bell discloses the claimed invention discussed in claim 19.
However, Smith, Song, Sumita, and Yuan do not explicitly disclose a second driver coupled with the third circuit, wherein the second driver is configured to receive the two non-overlapping clock signals, and drive the third circuit.
Nevertheless, Peng discloses a second driver coupled with the third circuit, wherein the second driver is configured to receive the two clock signals, and drive the third circuit (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith with the teachings of Peng to establish and maintain a stable and consistent clock signal to improve/ manage the operation of the circuit components.
However, Smith, Song, Peng, Sumita, and Yuan do not explicitly disclose wherein the second driver is configured to receive the two non-overlapping clock signals, and drive the third circuit.
Nevertheless, Bell discloses the two non-overlapping clock signals (as discussed above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Smith, Song, Peng, Sumita, and Yuan with the teachings of Bell to ensure that the clock signal alternates between two voltage levels while reducing the phase noise and jitter.
Response to Arguments
Applicant’s arguments, filed 07/23/2026 , with respect to claims 1-20 have been fully considered and are persuasive. The rejection of claims 1-20 have been withdrawn.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/SHARAH ZAAB/Examiner, Art Unit 2857
/Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857
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