DETAILED ACTION
This Office Action is responsive to the Applicant’s communication filed 17 July 2024. In view of this communication, claims 1-14 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 9-10 and 14 are objected to because of the following informalities:
Claim 9 recites that each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected with the circuit different from the second circuit, where “the circuit” refers to the circuit of claim 1 which is said to be different from the first circuit. Claim 9 should state explicitly that this circuit is also different from the second circuit before referring to it as such. Appropriate correction is required.
Claim 10 recites “the component in the second direction,” which should instead be “a component in the second direction.” Appropriate correction is required.
Claim 14 requires an indentation at line 8 of page 7. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 4, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishiyama (US 6107685 A), hereinafter referred to as Nishiyama, in view of Murakami (US 20230083442 A1), hereinafter referred to as Murakami.
Regarding claim 1, Nishiyama teaches a semiconductor device comprising:
a wiring substrate (8) (Fig. 6D and column 2, lines 30-32: circuit board 8);
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a semiconductor chip (7) mounted on the wiring substrate (8) via a plurality of protruding electrodes (6) (Fig. 6D and column 2, lines 30-32: semiconductor chip 7 mounted on the circuit board 8 via solder bumps 6 which protrude from the lower surface of the chip 7); and
a first insulating material (13) arranged between the semiconductor chip (7) and the wiring substrate (8), and sealing the plurality of protruding electrodes (6) (Fig. 6D and column 2, lines 55-60: resin 13 disposed in the space between chip 7 and board 9), wherein
the semiconductor chip (7) includes:
a semiconductor substrate (7) (column 2, line 30: Si wafer 7) having a first surface;
a first wiring layer (2, 4) formed on the first surface (column 2, lines 24-25: metal film 4 connected to electrode pads 2, which are mounted on the underside of the Si wafer 7);
a second insulating layer (5) arranged so as to cover the first wiring layer (2, 4) (column 2, lines 25-30: polyimide film 5 covering metal film 4), the second insulating layer (5) having a second surface facing the first surface of the semiconductor substrate (7) (see Fig. 6B) and a third surface opposite the second surface; and
the plurality of protruding electrodes (6) electrically connected with the first wiring layer (2, 4) (column 2, lines 20-25: bumps 6 connected to metal film 4 and electrodes 2),
wherein, in a plan view, the third surface of the second insulating layer includes:
a first side extending in a first direction (see for example the right side of area 20 in Fig. 1A);
a second side opposite the first side (for example, the left side in Fig. 1A);
a first region (1st region) located between the first side and the second side (annotated Fig. 1A, above, and column 7, lines 45-50: the area including small-diameter land terminals 22c located inside of intermediate terminals 22b constitutes the first region);
a second region (2nd region) located between the first side and the first region (1st region), and located next to the first region (1st region) (annotated Fig. 1A, above, and column 7, lines 40-50: the second region is defined as the area including intermediate-diameter terminals 22b and located inside large terminals 22a); and
a third region (3rd region) located between the first side and the second region (2nd region), and located next to the second region (2nd region) (annotated Fig. 1A, above, and column 7, lines 40-45: the third region is the area encompassing large-diameter terminals 22a on the peripheral edge of the chip and outside of terminals 22b),
wherein, in plan view, the plurality of protruding electrodes (6) includes (see column 6, lines 1-10: the electrodes 2 are arranged as shown in Fig. 1A and described in column 7, lines 40-50, which are referred to as elements 22a, 22b, and 22c, and are still mounted to a wiring board 8 with solder 6):
a plurality of first protruding electrodes (22c) arranged at positions overlapping the first region (1st region) (Fig. 1A and column 7, lines 45-50: small-diameter land terminals 22c located inside of intermediate terminals 22b);
a plurality of second protruding electrodes (22b) arranged at positions overlapping the second region (2nd region) (Fig. 1A and column 7, lines 40-50: intermediate-diameter terminals located inside large terminals 22a); and
a plurality of third protruding electrodes (22a) arranged at positions overlapping the third region (3rd region) (Fig. 1A and column 7, lines 40-50: intermediate-diameter terminals located inside large terminals 22a),
wherein the plurality of first protruding electrodes (22c) is arranged at a first pitch (Fig. 1A and column 7, lines 45-50: the pitch of the terminals 22c is 0.5mm),
wherein the plurality of second protruding electrodes (22b) is arranged at a second pitch (Fig. 1A and column 7, lines 44-45: the pitch of terminals 22b is 0.65mm),
wherein the plurality of third protruding electrodes (22a) is arranged at a third pitch different from each of the first pitch and the second pitch (Fig. 1A and column 7, lines 40-42: terminals 22a are arrange with a pitch of 0.8mm), and
wherein a component in a second direction, which is perpendicular to the first direction, of the second pitch is larger than a component in the second direction of the first pitch (column 7, lines 44-50: the pitch of terminals 22b is 0.65mm, larger than the pitch of terminals 22c, which is 0.5mm).
Nishiyama does not teach that each of the plurality of third protruding electrodes is electrically connected with a first circuit of the semiconductor chip, and that each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected with a circuit different from the first circuit. Murakami does teach that each of the plurality of third protruding electrodes (RIO) is electrically connected with a first circuit of the semiconductor chip (CM) (Murakami paragraph 65: a region RIO is provided on the periphery of the board which comprises pads connected to the input/output circuits of the chip CM), and that each of the plurality of first protruding electrodes (RMH) and the plurality of second protruding electrodes (RHU) is electrically connected with a circuit different from the first circuit (RIO) (Murakami paragraph 65: the pads in the regions RHU and RMH are connected to the hookup and memory hole regions, respectively).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to electrically connect the first, second, and third pads of Nishiyama to different circuits as taught by Murakami because providing different pads for each circuit enable connections to other circuitry on the component or circuitry on different components on the wiring board (Murakami paragraph 106).
Regarding claim 2, Nishiyama in view of Murakami teaches the semiconductor device according to claim 1, wherein the plurality of third protruding electrodes (22a) of the plurality of protruding electrodes includes a protruding electrode (22a) arranged at a position closest to the first side (see Fig. 1A and column 7, lines 40-50: the protruding electrodes 22a are arranged such that of the protruding electrodes 22a, 22b, 22c, the terminals 22a are closest to the sides of the chip).
Regarding claim 4, Nishiyama in view of Murakami teaches the semiconductor device according to claim 1, but does not teach that the plurality of second protruding electrodes is arranged in three or more rows in the second direction.
Murakami does teach that the plurality of second protruding electrodes is arranged in three or more rows in the second direction (Murakami Fig. 6 and paragraph 65: electrodes RHU are arranged in three rows).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second protruding electrodes of Nishiyama in view of Murakami in three or more rows as taught by Murakami because such an addition of a row of electrodes would constitute mere duplication of the electrodes already present and it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St Regis Paper Co. V. Bemis Co., 193 USPQ 8.
Regarding claim 9, Nishiyama in view of Murakami teaches the semiconductor device according to claim 1,
wherein, in plan view, the third surface of the second insulating layer further includes:
a third side extending in the second direction (see for example the top side in Fig. 1A); and
a fourth region (4th region) located between the third side and the first region (1st region) (annotated Fig. 1A, above),
wherein, in plan view, the plurality of protruding electrodes includes a plurality of fourth protruding electrodes (22c) arranged at positions overlapping the fourth region (4th region) (annotated Fig. 1A, above, and column 7, lines 40-50: terminals 22c arranged along the upper side of the chip 20),
and wherein the plurality of fourth protruding electrodes is arranged at the first pitch (see col. 7, lines 45-50).
Nishiyama in view of Murakami as modified above does not teach that each of the plurality of fourth protruding electrodes (22c) is electrically connected with a second circuit of the semiconductor chip, and that each of the plurality of first protruding electrodes (22c) and the plurality of second protruding electrodes (22b) is electrically connected with the circuit different from the second circuit.
Murakami does teach that each of the plurality of fourth protruding electrodes (PX) is electrically connected with a second circuit of the semiconductor chip (CM), and that each of the plurality of first protruding electrodes (RMH) and the plurality of second protruding electrodes (RHU) is electrically connected with the circuit different from the second circuit (Murakami paragraph 92: additional peripheral pads PX may be used as power supply pads).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the fourth electrodes of Nishiyama in view of Murakami to a second circuit of the semiconductor chip as taught by Murakami because providing different pads for each circuit enable connections to other circuitry on the component or circuitry on different components on the wiring board (Murakami paragraph 106).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishiyama in view of Murakami as applied to claims 1, 2, 4, and 9 above, and further in view of Mauclerc (US 20120111606 A1), hereinafter referred to as Mauclerc.
Regarding claim 5, Nishiyama in view of Murakami teaches the semiconductor device according to claim 1, but does not teach that each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is arranged in a staggered manner.
Mauclerc does teach that each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is arranged in a staggered manner (see Mauclerc Fig. 2 and paragraphs 63-65: each row of pads is staggered relative to the adjacent rows).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to stagger the first and second pads of Nishiyama in view of Murakami as taught by Mauclerc because it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claim(s) 10 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishiyama in view of Murakami and further in view of Ashida (US 20040124007 A1), hereinafter Ashida.
Regarding claim 10, Nishiyama in view of Murakami teaches the semiconductor device according to claim 9, but does not teach that the component in the second direction of the first pitch is longer than a component in the first direction of the first pitch.
Ashida does teach that the component in the second direction of the first pitch is longer than a component in the first direction of the first pitch (Ashida Fig. 1 and paragraph 18: the ratio of pitch P1 to P2 is 1.01 to 3, so that P1 is wider and P2 is narrower).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the first pitch of Nishiyama in view of Murakami as taught by Ashida such that the component in the second direction is longer than the component in the first direction because such an arrangement increases the distance between pads and wires, reducing the occurrence of short circuits due to shear in the printing of the solder (Ashida paragraph 19).
Regarding claim 14, Nishiyama teaches a semiconductor device comprising:
a wiring substrate (8) (Fig. 6D and column 2, lines 30-32: circuit board 8);
a semiconductor chip (7) mounted on the wiring substrate (8) via a plurality of protruding electrodes (6) (Fig. 6D and column 2, lines 30-32: semiconductor chip 7 mounted on the circuit board 8 via solder bumps 6 which protrude from the lower surface of the chip 7); and
a first insulating material (13) arranged between the semiconductor chip (7) and the wiring substrate (8), and sealing the plurality of protruding electrodes (6) (Fig. 6D and column 2, lines 55-60: resin 13 disposed in the space between chip 7 and board 9),
wherein the semiconductor chip (7) includes:
a semiconductor substrate (7) (column 2, line 30: Si wafer 7) having a first surface;
a first wiring layer (2, 4) formed on the first surface (column 2, lines 24-25: metal film 4 connected to electrode pads 2, which are mounted on the underside of the Si wafer 7);
a second insulating layer (5) arranged so as to cover the first wiring layer (2, 4) (column 2, lines 25-30: polyimide film 5 covering metal film 4), the second insulating layer (5) having a second surface facing the first surface of the semiconductor substrate (7) (see Fig. 6B) and a third surface opposite the second surface; and
the plurality of protruding electrodes (6) electrically connected with the first wiring layer (2, 4) (column 2, lines 20-25: bumps 6 connected to metal film 4 and electrodes 2),
wherein, in a plan view, the third surface of the second insulating layer includes:
a first side extending in a first direction (see for example the right side of area 20 in Fig. 1A);
a second side opposite the first side (for example, the left side in Fig. 1A);
a first region (1st region) located between the first side and the second side (annotated Fig. 1A, above, and column 7, lines 45-50: the area including small-diameter land terminals 22c located inside of intermediate terminals 22b constitutes the first region);
a second region (2nd region) located between the first side and the first region (1st region), and located next to the first region (1st region) (annotated Fig. 1A, above, and column 7, lines 40-50: the second region is defined as the area including intermediate-diameter terminals 22b and located inside large terminals 22a); and
a third region (3rd region) located between the first side and the second region (2nd region), and located next to the second region (2nd region) (annotated Fig. 1A, above, and column 7, lines 40-45: the third region is the area encompassing large-diameter terminals 22a on the peripheral edge of the chip and outside of terminals 22b),
wherein, in plan view, the plurality of protruding electrodes (6) includes (see column 6, lines 1-10: the electrodes 2 are arranged as shown in Fig. 1A and described in column 7, lines 40-50, which are referred to as elements 22a, 22b, and 22c, and are still mounted to a wiring board 8 with solder 6):
a plurality of first protruding electrodes (22c) arranged at positions overlapping the first region (1st region) (Fig. 1A and column 7, lines 45-50: small-diameter land terminals 22c located inside of intermediate terminals 22b);
a plurality of second protruding electrodes (22b) arranged at positions overlapping the second region (2nd region) (Fig. 1A and column 7, lines 40-50: intermediate-diameter terminals located inside large terminals 22a); and
a plurality of third protruding electrodes (22a) arranged at positions overlapping the third region (3rd region) (Fig. 1A and column 7, lines 40-50: intermediate-diameter terminals located inside large terminals 22a),
wherein the plurality of first protruding electrodes (22c) is arranged at a first pitch (Fig. 1A and column 7, lines 45-50: the pitch of the terminals 22c is 0.5mm),
wherein the plurality of second protruding electrodes (22b) is arranged at a second pitch (Fig. 1A and column 7, lines 44-45: the pitch of terminals 22b is 0.65mm),
wherein the plurality of third protruding electrodes (22a) is arranged at a third pitch different from each of the first pitch and the second pitch (Fig. 1A and column 7, lines 40-42: terminals 22a are arrange with a pitch of 0.8mm), and
Nishiyama does not teach that each of the plurality of third protruding electrodes is electrically connected with a first circuit of the semiconductor chip, and that each of the plurality of first protruding electrodes and the plurality of second protruding electrodes is electrically connected with a circuit different from the first circuit. Murakami does teach that each of the plurality of third protruding electrodes (RIO) is electrically connected with a first circuit of the semiconductor chip (CM) (Murakami paragraph 65: a region RIO is provided on the periphery of the board which comprises pads connected to the input/output circuits of the chip CM), and that each of the plurality of first protruding electrodes (RMH) and the plurality of second protruding electrodes (RHU) is electrically connected with a circuit different from the first circuit (RIO) (Murakami paragraph 65: the pads in the regions RHU and RMH are connected to the hookup and memory hole regions, respectively).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to electrically connect the first, second, and third pads of Nishiyama to different circuits as taught by Murakami because providing different pads for each circuit enable connections to other circuitry on the component or circuitry on different components on the wiring board (Murakami paragraph 106).
Nishiyama in view of Murakami teaches the semiconductor device according to claim 9, but does not teach that a component in a second direction, which is perpendicular to the first direction, of the second pitch is smaller than a component in the second direction of the first pitch.
Ashida does teach that a component in the second direction of the first pitch is longer than a component in the first direction of the first pitch (Ashida Fig. 1 and paragraph 18: the ratio of pitch P1 to P2 is 1.01 to 3, so that P1 is wider and P2 is narrower).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the first pitch of Nishiyama in view of Murakami as taught by Ashida such that the component in the second direction is longer than the component in the first direction because such an arrangement increases the distance between pads and wires, reducing the occurrence of short circuits due to shear in the printing of the solder (Ashida paragraph 19).
Allowable Subject Matter
Claims 6-8 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim that a minimum pitch between one of the plurality of first protruding electrodes and one, which is located next to the one of the plurality of first protruding electrodes, of the plurality of second protruding electrodes is equal to or greater than the first pitch, and that a minimum pitch between one of the plurality of third protruding electrodes and one, which is located next to the one of the plurality of third protruding electrodes, of the plurality of second protruding electrodes is equal to or greater than the first pitch.
Regarding claim 11, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in the claim that each of the plurality of first protruding electrodes is connected with either a power-supply potential supply path that supplies a power-supply potential to the circuit, or a reference potential supply path that supplies a reference potential to the circuit, and that the wiring substrate includes a second wiring layer where a plurality of terminals connected to any of the plurality of first protruding electrodes, the plurality of second protruding electrodes and the plurality of third protruding electrodes is arranged.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US 20220077116 A1)
Chen (US 10854566 B2)
Shi et al. (US 8970051 B2)
Hsieh (US 20110001239 A1)
Chang (US 20070080456 A1)
Matsuda (US 7193157 B2)
Chen (US 6940176 B2)
Tsai et al. (US 6787918 B1)
Miyagawa (US 20030114024 A1)
Kariyazaki (US 20030011071 A1)
Miyake et al. (US 20020022385 A1)
Newman (US 5490324 A)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John B Freal whose telephone number is (571)272-4056. The examiner can normally be reached Mon-Fri 7:00-3:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN B FREAL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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