Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
This is a response to Amendment/Req. Reconsideration-After Non-Final Rejection filed by Applicant on 08/03/2026.
Claims 1-20 are still pending.
Claims 1, 8 and 15 have been amended.
Response to Arguments
Claim Rejection Under 35 U.S.C. §102:
Applicant’s arguments, see pages 5-6, filed 08/03/2026, with respect to the rejection(s) of claims 1-20 being rejected under AIA 35 U.S.C. § 102(a)(1)/102(a)(2) as unpatentable over Farkas et al. (US 2008/0087461), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Adler et al. US 2021/0014979 in combination with the previously cited prior arts of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Farkas et al. US 2008/0087461 (Previously Cited; Hereinafter Farkas) in view of Adler et al. US 2021/0014979 (Newly Cited; Hereinafter Adler).
Regarding claim 1, Farkas teaches a printed circuit board (Figs. 1, 2; printed circuit board, 5), comprising:
a via (Figs. 1, 2; board via, 10) configured to provide electrical connectivity between layers of the printed circuit board (Figs. 1, 2; [0017]; board via, 10; “ FIG. 1 further includes a board via 10 for providing electrical communication between layers of the PCB 5”) and having at least a portion of the via (Figs. 1, 2; board via, 10) backdrilled (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) resulting in a backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling); and
a test coupon (Figs. 1, 2; test coupon, 12) configured to determine whether the backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) is according to a specification (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Farkas does not specifically teach wherein the test coupon is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality.
However, Adler does teach wherein the test coupon (Figs. 1-4; [0051, 0104]; test coupon) is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality (Figs. 1-4; [0051, 0104]; “ back-drilling process for quality control purpose”).
It would have been obvious before the effective filing date of the claimed invention to modify the combination impdance/back drill coupon of Farkas by implementing the teachings of Adler regarding wherein the test coupon is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality; in order to “inspect a printed circuit board to measure a number of dimensions at a number of pre-determined locations of the printed circuit board” (See Adler; Abstract).
Regarding claim 2, the combination of Farkas and Adler teaches the printed circuit board of claim 1, wherein Farkas further teaches wherein the specification includes a backdrill hole depth (Figs. 3a, 4a, 5a; Abstract; [0019-0027]; back drilling; From Abstract: “A test coupon on a printed circuit board used for verifying that vias in the printed circuit board are back drilled to a proper predetermined depth.”).
Regarding claim 3, the combination of Farkas and Adler teaches the printed circuit board of claim 1, wherein Farkas further teaches wherein if the backdrill hole is according to the specification, then production of the printed circuit board is initiated (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 4, the combination of Farkas and Adler teaches the printed circuit board of claim 1, wherein Farkas further teaches wherein the test coupon (Figs. 1, 2; test coupon, 12) includes a test point (Figs. 1, 2; [0019-0027]; test coupon, 12).
Regarding claim 5, the combination of Farkas and Adler teaches the printed circuit board of claim 1, wherein Farkas further teaches wherein a short/open test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 6, the combination of Farkas and Adler teaches the printed circuit board of claim 1, wherein Farkas further teaches wherein a ground test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 7, the combination of Farkas and Adler teaches the printed circuit board of claim 1, wherein Farkas further teaches wherein an impedance test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 8, Farkas teaches an information handling system (Figs. 1, 2) comprising:
a printed circuit board (Figs. 1, 2; printed circuit board, 5) comprising:
a via (Figs. 1, 2; board via, 10) configured to provide electrical connectivity between layers of the printed circuit board (Figs. 1, 2; [0017]; board via, 10; “ FIG. 1 further includes a board via 10 for providing electrical communication between layers of the PCB 5”) and having at least a portion of the via (Figs. 1, 2; board via, 10) backdrilled (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) resulting in a backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling); and
a test coupon (Figs. 1, 2; test coupon, 12) configured to determine whether the backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) is according to a specification (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Farkas does not specifically teach wherein the test coupon is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality.
However, Adler does teach wherein the test coupon (Figs. 1-4; [0051, 0104]; test coupon) is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality (Figs. 1-4; [0051, 0104]; “ back-drilling process for quality control purpose”).
It would have been obvious before the effective filing date of the claimed invention to modify the combination impdance/back drill coupon of Farkas by implementing the teachings of Adler regarding wherein the test coupon is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality; in order to “inspect a printed circuit board to measure a number of dimensions at a number of pre-determined locations of the printed circuit board” (See Adler; Abstract).
Regarding claim 9, the combination of Farkas and Adler teaches the information handling system of claim 8, wherein Farkas further teaches wherein the specification includes a backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 10, the combination of Farkas and Adler teaches the information handling system of claim 8, wherein Farkas further teaches wherein if the backdrill hole is according to the specification, then production of the printed circuit board is initiated (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 11, the combination of Farkas and Adler teaches the information handling system of claim 8, wherein Farkas further teaches wherein the test coupon (Figs. 1, 2; test coupon, 12) includes a test point (Figs. 1, 2; [0019-0027]; test coupon, 12).
Regarding claim 12, the combination of Farkas and Adler teaches the information handling system of claim 8, wherein Farkas further teaches wherein a short/open test is used to determine whether the backdrill hole is according to the specification (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 13, the combination of Farkas and Adler teaches the information handling system of claim 8, wherein Farkas further teaches wherein a ground test is used to determine whether the backdrill hole is according to the specification (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 14, the combination of Farkas and Adler teaches the information handling system of claim 8, wherein Farkas further teaches wherein an impedance test is used to determine whether the backdrill hole is according to the specification (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 15, Farkas teaches a method (Figs. 1, 2) comprising:
providing a printed circuit board (Figs. 1, 2; printed circuit board, 5) comprising:
a via (Figs. 1, 2; board via, 10) providing electrical connectivity between layers of the printed circuit board (Figs. 1, 2; [0017]; board via, 10; “ FIG. 1 further includes a board via 10 for providing electrical communication between layers of the PCB 5”) and having at least a portion of the via (Figs. 1, 2; board via, 10) backdrilled (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) resulting in a backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling); and
a test coupon (Figs. 1, 2; test coupon, 12) providing electrical communication for determining whether the backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) is according to a specification (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Farkas does not specifically teach wherein the test coupon is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality.
However, Adler does teach wherein the test coupon (Figs. 1-4; [0051, 0104]; test coupon) is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality (Figs. 1-4; [0051, 0104]; “ back-drilling process for quality control purpose”).
It would have been obvious before the effective filing date of the claimed invention to modify the combination impdance/back drill coupon of Farkas by implementing the teachings of Adler regarding wherein the test coupon is used to determine whether the backdrill hole is within a pre-defined width verifying backdrill quality; in order to “inspect a printed circuit board to measure a number of dimensions at a number of pre-determined locations of the printed circuit board” (See Adler; Abstract).
Regarding claim 16, the combination of Farkas and Adler teaches the method of claim 15, wherein Farkas further teaches wherein the specification includes a backdrill hole depth (Figs. 3a, 4a, 5a; Abstract; [0019-0027]; back drilling; From Abstract: “A test coupon on a printed circuit board used for verifying that vias in the printed circuit board are back drilled to a proper predetermined depth.”).
Regarding claim 17, the combination of Farkas and Adler teaches the method of claim 15, wherein Farkas further teaches wherein if the backdrill hole is according to the specification, then a short/open test passes (Figs. 3a, 4a, 5a; Abstract; [0019-0027]; back drilling; From Abstract: “A test coupon on a printed circuit board used for verifying that vias in the printed circuit board are back drilled to a proper predetermined depth.”).
Regarding claim 18, the combination of Farkas and Adler teaches the method of claim 15, wherein Farkas further teaches wherein a short/open test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 19, the combination of Farkas and Adler teaches the method of claim 15, wherein Farkas further teaches wherein a ground test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 20, the combination of Farkas and Adler teaches the method of claim 15, wherein Farkas further teaches wherein an impedance test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ziegler, IV et al. US 2022/0200179 - An information handling system includes first and second printed circuit boards (PCBs), and first and second connectors. The first PCB includes a first top surface, a first bottom, and a first plurality of side surfaces extending between the first top and first bottom surfaces. The first connector is embedded within the first PCB, and extends from the first bottom surface toward the first top surface. A first height of the first connector is substantially equal to a first thickness of the first PCB. The second PCB includes a second top surface, a second bottom, and a second plurality of side surfaces extending between the second top and second bottom surfaces.
Laurx et al. US 2016/0261075 - A connector system includes a connector mounted on a circuit board. The circuit board has deeper backdrilled vias and the connector has modified signal terminal that can mate with the backdrilled vias so as to provide a surprising increase in the performance of signal traces provided in the top layers of the circuit board.
Chan et al. US 2008/0227311 - An electrical signal connection, an electrical signaling system, and a method of connecting printed circuit boards. The electrical signal connection having a first conductive via and a second conductive via disposed in a first printed circuit board. A first conductive trace with a first end and a second end has the first end electrically coupled to the first conductive via at a first distance from the top surface of the first printed circuit board. The second end of the first conductive via is electrically coupled to the second printed circuit board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAUL J RIOS RUSSO whose telephone number is (571)270-3459. The examiner can normally be reached Monday-Friday: 10am-6pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RAUL J RIOS RUSSO/Examiner, Art Unit 2858
Prosecution Insights