Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/17/2024 has been considered by the examiner.
Oath/Declaration
Oath/Declaration as file 07/17/2024 is noted by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Farkas et al. US 2008/0087461 (Hereinafter Farkas).
Regarding claim 1, Farkas teaches a printed circuit board (Figs. 1, 2; printed circuit board, 5), comprising:
a via (Figs. 1, 2; board via, 10) configured to provide electrical connectivity between layers of the printed circuit board (Figs. 1, 2; [0017]; board via, 10; “ FIG. 1 further includes a board via 10 for providing electrical communication between layers of the PCB 5”) and having at least a portion of the via (Figs. 1, 2; board via, 10) backdrilled (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) resulting in a backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling); and
a test coupon (Figs. 1, 2; test coupon, 12) configured to determine whether the backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) is according to a specification (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 2, Farkas further teaches the printed circuit board of claim 1, wherein the specification includes a backdrill hole depth (Figs. 3a, 4a, 5a; Abstract; [0019-0027]; back drilling; From Abstract: “A test coupon on a printed circuit board used for verifying that vias in the printed circuit board are back drilled to a proper predetermined depth.”).
Regarding claim 3, Farkas further teaches the printed circuit board of claim 1, wherein if the backdrill hole is according to the specification, then production of the printed circuit board is initiated (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 4, Farkas further teaches the printed circuit board of claim 1, wherein the test coupon (Figs. 1, 2; test coupon, 12) includes a test point (Figs. 1, 2; [0019-0027]; test coupon, 12).
Regarding claim 5, Farkas further teaches the printed circuit board of claim 1, wherein a short/open test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 6, Farkas further teaches the printed circuit board of claim 1, wherein a ground test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 7, Farkas further teaches the printed circuit board of claim 1, wherein an impedance test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 8, Farkas teaches an information handling system (Figs. 1, 2) comprising:
a printed circuit board (Figs. 1, 2; printed circuit board, 5) comprising:
a via (Figs. 1, 2; board via, 10) configured to provide electrical connectivity between layers of the printed circuit board (Figs. 1, 2; [0017]; board via, 10; “ FIG. 1 further includes a board via 10 for providing electrical communication between layers of the PCB 5”) and having at least a portion of the via (Figs. 1, 2; board via, 10) backdrilled (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) resulting in a backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling); and
a test coupon (Figs. 1, 2; test coupon, 12) configured to determine whether the backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) is according to a specification (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 9, Farka further teaches the information handling system of claim 8, wherein the specification includes a backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 10, Farka further teaches the information handling system of claim 8, wherein if the backdrill hole is according to the specification, then production of the printed circuit board is initiated (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 11, Farka further teaches the information handling system of claim 8, wherein the test coupon (Figs. 1, 2; test coupon, 12) includes a test point (Figs. 1, 2; [0019-0027]; test coupon, 12).
Regarding claim 12, Farka further teaches the information handling system of claim 8, wherein a short/open test is used to determine whether the backdrill hole is according to the specification (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 13, Farka further teaches the information handling system of claim 8, wherein a ground test is used to determine whether the backdrill hole is according to the specification (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 14, Farka further teaches the information handling system of claim 8, wherein an impedance test is used to determine whether the backdrill hole is according to the specification (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 15, Farkas teaches a method (Figs. 1, 2) comprising:
providing a printed circuit board (Figs. 1, 2; printed circuit board, 5) comprising:
a via (Figs. 1, 2; board via, 10) providing electrical connectivity between layers of the printed circuit board (Figs. 1, 2; [0017]; board via, 10; “ FIG. 1 further includes a board via 10 for providing electrical communication between layers of the PCB 5”) and having at least a portion of the via (Figs. 1, 2; board via, 10) backdrilled (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) resulting in a backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling); and
a test coupon (Figs. 1, 2; test coupon, 12) providing electrical communication for determining whether the backdrill hole (Figs. 3a, 4a, 5a; [0019-0027]; back drilling) is according to a specification (Figs. 3a, 4a, 5a; [0019-0027]; test coupon; From [0020]: “FIGS. 3a, 4a, and 5a illustrate a back drilling process with a test coupon, wherein the test coupon can be used to confirm that the vias of the board have been back drilled to the proper pre-determined depth.”).
Regarding claim 16, Farkas further teaches the method of claim 15, wherein the specification includes a backdrill hole depth (Figs. 3a, 4a, 5a; Abstract; [0019-0027]; back drilling; From Abstract: “A test coupon on a printed circuit board used for verifying that vias in the printed circuit board are back drilled to a proper predetermined depth.”).
Regarding claim 17, Farkas further teaches the method of claim 15, wherein if the backdrill hole is according to the specification, then a short/open test passes (Figs. 3a, 4a, 5a; Abstract; [0019-0027]; back drilling; From Abstract: “A test coupon on a printed circuit board used for verifying that vias in the printed circuit board are back drilled to a proper predetermined depth.”).
Regarding claim 18, Farkas further teaches the method of claim 15, wherein a short/open test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 19, Farkas further teaches the method of claim 15, wherein a ground test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Regarding claim 20, Farkas further teaches the method of claim 15, wherein an impedance test is used to determine whether the backdrill hole is according to a pre-defined backdrill hole depth (Figs. 3a, 4a, 5a; [0019-0027]; back drilling).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wilkinson et al. US 2021/0153359 - A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions.
Wilkinson et al. US 2023/0156928 - A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions.
Chu et al. US 2023/0345634 - An information handling system includes a printed circuit board having a signal via fabricated through the printed circuit board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAUL J RIOS RUSSO whose telephone number is (571)270-3459. The examiner can normally be reached Monday-Friday: 10am-6pm, EST.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858
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