DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Objections
Claim is objected to because of the following informalities:
Claim 5, line 1-2 recites “the margin portions further comprises” which has a grammatical error. It should recite “the margin portions further comprise”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18, line 8 recites “second pads .. compressing the epoxy solders on the first pads”. Compressing can mean squeezed structure or an act rather than a structure. Therefore, it is unclear, and the scope of the claim is unclear.
For, examination purpose compressing is regarded as a compressing structure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 14 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM; NAMHOON (US 20220013501 A1) “KIM et al.”.
Regarding Independent Claim 14, KIM et al. Figs. 1A, 3, 4A-4B a semiconductor package comprising:
an insulating layer 180 (“a first protective layer 180” ¶ [0028]);
first pads 160 (“a first redistribution pattern 160” ¶ [0028]) respectively surrounded by the insulating layer 180;
second pads 320 (“a pillar pattern 320” ¶ [0043]) electrically connected to the first pads 160;
solders 310 between and connected to the first pads 160 and the second pads 320, and respectively surrounded by the insulating layer 180 (“The solder pattern 310 may also be provided in the first opening 189 of the first protective layer 180 and may be in contact with the inner sidewall 180c of the first protective layer 180.” ¶ [0043]); and
an underfill 420 (“underfill layer 420” ¶ [0050]) on an upper surface of the insulating layer 180 and surrounding each of the second pads 320,
wherein a level of lower surfaces of the second pads 320 is lower than a level of the upper surface of the insulating layer (“the bottom surface 320b of the pillar pattern 320 may be disposed at a lower level than the top surface 180a of the first protective layer 180.” ¶ [0044]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, 9, 11-12, are rejected under 35 U.S.C. 103 as being unpatentable over KIM; NAMHOON (US 20220013501 A1) “KIM et al.” in view of Fujimori, Joji (US 20040046252 A1) “Fujimori et al.”.
Regarding Independent Claim 1, KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B discloses a semiconductor package (“a semiconductor package” ¶ [0025]) comprising:
an insulating layer (“a first protective layer 180” ¶ [0028]);
first pads (“a first redistribution pattern 160” ¶ [0028]) respectively surrounded by the insulating layer (Fig. 1A shows 180 covering 160);
second pads (“the pillar pattern 320 may be disposed between the solder pattern 310 and the second chip pad 250” ¶ [0044]) electrically connected to the first pads (“the pillar pattern 320 may be disposed between the solder pattern 310 and the second chip pad 250” ¶ [0044]);
solders between and connected to the first pads and the second pads, and respectively surrounded by the insulating layer (“The solder pattern 310 may be provided in the first hole 169 of the first redistribution pattern 160 and may cover the inner sidewall 160c of the first redistribution pattern 160. For example, the solder pattern 310 may be in contact with the inner sidewall 160c of the first redistribution pattern 160. The solder pattern 310 may also be provided in the first opening 189 of the first protective layer 180 and may be in contact with the inner sidewall 180c of the first protective layer 180.” ¶ [0043]);
However, KIM et al. does not disclose margin portions comprising an insulating material, surrounding the solders, and respectively surrounded by the insulating layer.
In the similar field of endeavor of semiconductor package Fujimori et al. Figs. 2-6 discloses margin portions (“thermosetting resin 171” ¶ [0083]) comprising an insulating material (“the thermosetting resin 171 is cured” ¶ [0157]; cure resin is an insulating material), surrounding the solders 161, and respectively surrounded by the insulating layer 81 (“as shown in FIG. 5, the thermosetting resin 171 is placed as an underfill between the solder balls 161 and the semiconductor substrate 61 as well as between the sidewalls of the film-like solder resist 81 and the semiconductor substrate 61.” ¶ [0085]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. including the margin layer of Fujimori et al. in order to form the cured resin member that supports the solder ball. Since a single heating process suffices to form the solder ball and the cured resin member simultaneously, manufacturing steps are simplified. Further, the cured resin member is placed between the solder ball and the electrode pad, so that it serves to reinforce the strength of connection between the solder ball and the electrode pad. (Fujimori et al. ¶ [0021]).
Regarding Claim 2, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 1. However, KIM et al. does not disclose wherein the margin portions respectively surround the solders and separate the first pads from the insulating layer.
In the similar field of endeavor of semiconductor package Fujimori et al. Figs. 2-6 discloses wherein the margin portions 171 respectively surround the solders 161 and separate the first pads 71 from the insulating layer 81 (Figs. 3-5 shows the margin portions 171 respectively surround the solders 161 and separate the first pads 71 from the insulating layer 81).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. including the margin layer of Fujimori et al. in order to form the cured resin member that supports the solder ball. Since a single heating process suffices to form the solder ball and the cured resin member simultaneously, manufacturing steps are simplified. Further, the cured resin member is placed between the solder ball and the electrode pad, so that it serves to reinforce the strength of connection between the solder ball and the electrode pad. (Fujimori et al. ¶ [0021]).
Regarding Claim 3, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 1. KIM et al. further discloses, an insulating material of the insulating layer (“the first protective layer 180 may include a photosensitive polymer or a photoimageable dielectric material. For example, the photosensitive polymer or the photoimageable dielectric material may include at least one of photosensitive polyimide, polybenzoxazole, a phenol-based polymer, or a benzocyclobutene-based polymer.” ¶ [0038]).
However, KIM et al. does not disclose wherein the insulating material of the margin portions is different from an insulating material of the insulating layer.
In the similar field of endeavor of semiconductor package Fujimori et al. Figs. 2-6 discloses the insulating material of the margin portions (“the thermosetting resin 171 is cured” ¶ [0157]; cure resin is an insulating material).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. including the margin layer of Fujimori et al. which results in the insulating material of the margin portions is different from an insulating material of the insulating layer in order to form the cured resin member that supports the solder ball. Since a single heating process suffices to form the solder ball and the cured resin member simultaneously, manufacturing steps are simplified. Further, the cured resin member is placed between the solder ball and the electrode pad, so that it serves to reinforce the strength of connection between the solder ball and the electrode pad. (Fujimori et al. ¶ [0021]).
Regarding Claim 4, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 1. KIM et al. further discloses, wherein the insulating layer comprises at least one from among a build-up film, photosensitive polyimide (PSPI), and a photo imageable dielectric (PID) (“the first protective layer 180 may include a photosensitive polymer or a photoimageable dielectric material. For example, the photosensitive polymer or the photoimageable dielectric material may include at least one of photosensitive polyimide, polybenzoxazole, a phenol-based polymer, or a benzocyclobutene-based polymer.” ¶ [0038]).
However, KIM et al. does not disclose wherein the insulating material of the margin portions comprises an epoxy resin.
In the similar field of endeavor of semiconductor package Fujimori et al. Figs. 2-6 discloses wherein the insulating material of the margin portions comprises an epoxy resin (“An epoxy-type resin may be used as the thermosetting resin 171” ¶ [0084]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. including the margin layer of Fujimori et al. which results in the insulating material of the margin portions is different from an insulating material of the insulating layer in order to form the cured resin member that supports the solder ball. Since a single heating process suffices to form the solder ball and the cured resin member simultaneously, manufacturing steps are simplified. Further, the cured resin member is placed between the solder ball and the electrode pad, so that it serves to reinforce the strength of connection between the solder ball and the electrode pad. (Fujimori et al. ¶ [0021]).
Regarding Claim 6, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 1. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, further comprising an underfill (“A second underfill layer 420 may be provided in a second gap region between the top surface of the first semiconductor chip 100 and the bottom surface of the second semiconductor chip 200.” ¶ [0050]) surrounding each of the second pads (Fig. 1A shows 420 surrounding 320).
Regarding Claim 7, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 6. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein the underfill (“A second underfill layer 420 may be provided in a second gap region between the top surface of the first semiconductor chip 100 and the bottom surface of the second semiconductor chip 200.” ¶ [0050]) is spaced apart (As the solder 310 is in the gap 169 or 189 therefore separated from 420) from the solders (“The solder pattern 310 may be provided in the first hole 169 of the first redistribution pattern 160 and may cover the inner sidewall 160c of the first redistribution pattern 160. For example, the solder pattern 310 may be in contact with the inner sidewall 160c of the first redistribution pattern 160. The solder pattern 310 may also be provided in the first opening 189 of the first protective layer 180 and may be in contact with the inner sidewall 180c of the first protective layer 180” ¶ [0043]).
Regarding Claim 9, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 6. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein the underfill 420 is on an upper surface of the insulating layer (“the second underfill layer 420 disposed on the top surface 180a of the first protective layer 180” ¶ [0051]), and
wherein a level of lower surfaces of the second pads 320 is lower than a level of the upper surface of the insulating layer (“the bottom surface 320b of the pillar pattern 320 may be disposed at a lower level than the top surface 180a of the first protective layer 180.” ¶ [0044]).
Regarding Claim 11, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 1. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, further comprising semiconductor chips (“the first and second semiconductor chips 100 and 200” ¶ [0043]),
wherein the insulating layer 180, the first pads 160, and the second pads 320 are between the semiconductor chips 100 & 200 (“The bump structure 300 may be disposed between the first and second semiconductor chips 100 and 200 and may be electrically connected to the first and second semiconductor chips 100 and 200. The bump structure 300 may include a solder pattern 310 and a pillar pattern 320. The solder pattern 310 may be provided in the first hole 169 of the first redistribution pattern 160 and may cover the inner sidewall 160c of the first redistribution pattern 160. For example, the solder pattern 310 may be in contact with the inner sidewall 160c of the first redistribution pattern 160. The solder pattern 310 may also be provided in the first opening 189 of the first protective layer 180 and may be in contact with the inner sidewall 180c of the first protective layer 180.” ¶ [0043]).
Regarding Claim 12, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 11. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein one of the semiconductor chips comprises:
a semiconductor substrate (“semiconductor substrate 110” ¶ [0028]);
a device layer comprising an interconnection structure, the device layer on a front surface of the semiconductor substrate (“The first circuit layer 120 may be disposed on the bottom surface 110b of the first semiconductor substrate 110. The first circuit layer 120 may include a first insulating layer 121, first integrated circuits 123, and a first interconnection structure 125, as illustrated in FIG. 1B.” ¶ [0029]);
through-electrodes penetrating through the semiconductor substrate (“The first through-structure 140 may penetrate the top surface 110a and the bottom surface 110b of the first semiconductor substrate 110” ¶ [0033]) and electrically connected to the first pads (“the first redistribution pattern 160 may be disposed on a top surface of the first through-structure 140 and may be in contact with the top surface of the first through-structure 140.” ¶ [0035]); and
a rear insulating layer on a rear surface of the semiconductor substrate (“a first upper insulating layer 170 may further be disposed between the top surface 110a of the first semiconductor substrate 110 and the first redistribution pattern 160” ¶ [0034]),
wherein the insulating layer 180 is on a rear surface of the rear insulating layer 170 (“the first protective layer 180 may cover the top surface and an outer sidewall of the first redistribution pattern 160 and a top surface of the first upper insulating layer 170. The first protective layer 180 may contact the top surface and an outer sidewall of the first redistribution pattern 160 and a top surface of the first upper insulating layer 170.” ¶ [0038]).
Claims 5 are rejected under 35 U.S.C. 103 as being unpatentable over KIM; NAMHOON (US 20220013501 A1) “KIM et al.” in view of Fujimori, Joji (US 20040046252 A1) “Fujimori et al.” further in view of Hirano; Koichi (US 20080142966 A1) “Hirano et al.”.
Regarding Claim 5, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 1. However, KIM et al. does not disclose, wherein the margin portions further comprise solder particles.
In the similar field of endeavor of semiconductor package Fujimori et al. Figs. 2-6 discloses the margin portions (“An epoxy-type resin may be used as the thermosetting resin 171. The ratio of the solder to the thermosetting resin 171 in the solder paste 90 may be adjusted within a range of 70-92 wt % of solder and 8-25 wt % of thermosetting resin 171.” ¶ [0084]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. including the margin layer of Fujimori et al. in order to form the cured resin member that supports the solder ball. Since a single heating process suffices to form the solder ball and the cured resin member simultaneously, manufacturing steps are simplified. Further, the cured resin member is placed between the solder ball and the electrode pad, so that it serves to reinforce the strength of connection between the solder ball and the electrode pad. (Fujimori et al. ¶ [0021]).
However, Fujimori et al. does not disclose, wherein the margin portions further comprise solder particles.
In the similar field of endeavor of semiconductor package Hirano et al. Figs. 2A(a)-2A(d) discloses wherein the margin portions further comprise solder particles (“The moving metal particles 1,1' are allowed to self-assemble into a region between each electrode 7 of the semiconductor chip 8 and each electrode 5 of the circuit substrate 6 as shown in FIG. 2A(c) due to high wettability of the electrodes 5 and 7” ¶ [0138]; “A metal component constituting the metal particles 1,1' melts as the temperature rises. The melted metal component agglomerates and grows so as to interconnect each electrode 7 of the semiconductor chip 8 and each electrode 5 of the circuit substrate 6. The melting of the metal component causes the melting of the metal layer 2 of the metal particle 1. Thus, the first component 3a (dicyandiamide) that has been contained in the metal particles 1 is released into the second component 3b (bisphenol A type epoxy resin), which leads to a contact of the first component 3a and the second component 3b. This contact initiates a curing reaction between the first component 3a and the second component 3b, and thereby a thermoset resin 3c is formed. The formation of the thermoset resin 3c causes a viscosity rise of the composition 4. This means that the viscosity of the composition 4 is kept low while the metal particles 1,1' are moving since the curing reaction is not yet initiated during the starting phase of the heating.” ¶ [0139]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. including the margin layer of Fujimori et al. with the solder particles in the margin of Hirano et al. in order to provide a composition that can solve a problem attributable to the viscosity increase. Also, another object of the present invention is to provide a satisfactory flip chip mounting process and a satisfactory bump-forming process in terms of a prevented short-circuit and thus in terms of a connecting reliability (Hirano et al. ¶ [0018]) and to reduce a amount of the residual metal particles that are left outside of electrodes or outside of the region between the opposed electrodes, which will lead to a prevention of the short-circuit. As a result, an excellent connecting reliability between the opposed electrodes is achieved (Hirano et al. ¶ [0067]).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over KIM; NAMHOON (US 20220013501 A1) “KIM et al.” in view of Fujimori, Joji (US 20040046252 A1) “Fujimori et al.” further in view of Huang; Han-Hsiang (US 20230411345 A1) “Huang et al.”.
Regarding Claim 8, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 6. However, KIM et al. does not disclose, wherein a thickness of each of the second pads is greater than a thickness of each of the first pads.
In the similar field of endeavor of semiconductor package Huang et al. Figs. 3A-3H and 7A-7B discloses wherein a thickness (“The total height of each second metallic bump structure may be in a range from 10 microns to 100 microns” ¶ [0078]) of each of the second pads (“a second metallic bump structure 30” ¶ [0075]) is greater (10-100um> 250nm-5.5um) than a thickness (“The thickness of a horizontally-extending portion of the first metallic seed layer 21 may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses may also be used.” ¶ [0045]; “The thickness of the nickel plate portion 24 may be in a range from 200 nm to 5 microns, such as from 500 nm to 2 microns, although lesser and greater thicknesses may also be used” [0047]) of each of the first pads (“configuration of the first metallic bump structure 20 may be the same as the base bump plate (21, 24)” ¶ [0075]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. as modified by Fujimori et al. with thickness of each of the second pads is greater than a thickness of each of the first pads of Huang et al. in order to provide bridging-resistant bump structures that limits a bump shift range, and avoids bump bridging that leads to unintended electrical connection between bump structures (Huang et al. ¶ [0177]).
Regarding Claim 10, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 1. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein each of the first pads 160 comprises copper or a copper alloy (“The first redistribution pattern 160 may include a seed pattern 161 and a conductive pattern 162. For example, the seed pattern 161 may include at least one of titanium or copper. The bottom surface of the first redistribution pattern 160 may mean a bottom surface of the seed pattern 161. The conductive pattern 162 may be disposed on the seed pattern 161, and may be in contact with a top surface of the seed pattern 161. The conductive pattern 162 may include a metal such as copper, nickel, or any alloy thereof.” ¶ [0037]),
wherein each of the second pads comprises copper or a copper alloy (“The pillar pattern 320 may include a conductive material such as copper.” ¶ [0044]), and
wherein the solders are in direct contact with the copper or copper alloy of the first pads (“the solder pattern 310 may be in good contact with the inner sidewall 160c of the first redistribution pattern 160” ¶ [0046]).
However, KIM et al. does not disclose, the solders are in direct contact with the copper or copper alloy of the second pads.
In the similar field of endeavor of semiconductor package Huang et al. Figs. 3A-3H and 7A-7B discloses the solders (“solder material portions 40” ¶ [0164]) are in direct contact (Fig. 7A shows 40 in direct contact with 36 of 30) with the copper or copper alloy of the second pads (“each second metallic bump structure 30 may comprise a first copper plate portion 32, a nickel plate portion 34, and a second copper plate portion 36” ¶ [0165]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. as modified by Fujimori et al. with the solders are in direct contact with the copper or copper alloy of the second pads of Huang et al. in order to provide bridging-resistant bump structures that limits a bump shift range, and avoids bump bridging that leads to unintended electrical connection between bump structures (Huang et al. ¶ [0177]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over KIM; NAMHOON (US 20220013501 A1) “KIM et al.” in view of Fujimori, Joji (US 20040046252 A1) “Fujimori et al.” further in view of CHOI; Minjung (US 20210043591 A1) “CHOI et al.”
Regarding Claim 13, KIM et al. as modified by Fujimori et al. discloses the limitations of claim 11. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein one of the semiconductor chips comprises:
a semiconductor substrate (“semiconductor substrate 110” ¶ [0028]); and
a device layer comprising an interconnection structure, the device layer on a front surface of the semiconductor substrate (“The first circuit layer 120 may be disposed on the bottom surface 110b of the first semiconductor substrate 110. The first circuit layer 120 may include a first insulating layer 121, first integrated circuits 123, and a first interconnection structure 125, as illustrated in FIG. 1B.” ¶ [0029]),
However, KIM et al. does not disclose wherein the interconnection structure comprises:
an interconnection layer; and
a conductive pattern electrically connecting the interconnection layer to the second pads, and
wherein the conductive pattern is thicker than the interconnection layer.
In the similar field of endeavor of semiconductor package CHOI et al. Figs. 1-4 discloses wherein the interconnection structure comprises:
an interconnection layer (“a plurality of middle interconnections 41 and 42” ¶ [0016]); and
a conductive pattern (“a pad 61” ¶ [0016]), and
wherein the conductive pattern 61 (“The pad 61 may exhibit a second thickness d2” ¶ [0023]) is thicker (“The second thickness d2 may be greater than the first thickness d1.” ¶ [0025]) than the interconnection layer (“interconnections 42 may exhibit a first thickness d1” ¶ [0019]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. as modified by Fujimori et al. with the interconnection structure of CHOI et al. electrically connecting the interconnection layer to the second pads 320 of KIM et al. in order to obtain a semiconductor device having excellent current drivability, a high signal transmission rate, and high physical/chemical reliability can be implemented (CHOI et al. ¶ [0080]).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over KIM; NAMHOON (US 20220013501 A1) “KIM et al.” in view of Huang; Han-Hsiang (US 20230411345 A1) “Huang et al.”.
Regarding Claim 15, KIM et al. discloses the limitations of claim 14. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein the underfill (“A second underfill layer 420 may be provided in a second gap region between the top surface of the first semiconductor chip 100 and the bottom surface of the second semiconductor chip 200.” ¶ [0050]) is spaced apart (As the solder 310 is in the gap 169 or 189 therefore separated from 420) from the solders (“The solder pattern 310 may be provided in the first hole 169 of the first redistribution pattern 160 and may cover the inner sidewall 160c of the first redistribution pattern 160. For example, the solder pattern 310 may be in contact with the inner sidewall 160c of the first redistribution pattern 160. The solder pattern 310 may also be provided in the first opening 189 of the first protective layer 180 and may be in contact with the inner sidewall 180c of the first protective layer 180” ¶ [0043]).
However, KIM et al. does not disclose, wherein a thickness of each of the second pads is greater than a thickness of each of the first pads.
In the similar field of endeavor of semiconductor package Huang et al. Figs. 3A-3H and 7A-7B discloses wherein a thickness (“The total height of each second metallic bump structure may be in a range from 10 microns to 100 microns” ¶ [0078]) of each of the second pads (“a second metallic bump structure 30” ¶ [0075]) is greater (10-100um> 250nm-5.5um) than a thickness (“The thickness of a horizontally-extending portion of the first metallic seed layer 21 may be in a range from 50 nm to 500 nm, although lesser and greater thicknesses may also be used.” ¶ [0045]; “The thickness of the nickel plate portion 24 may be in a range from 200 nm to 5 microns, such as from 500 nm to 2 microns, although lesser and greater thicknesses may also be used” [0047]) of each of the first pads (“configuration of the first metallic bump structure 20 may be the same as the base bump plate (21, 24)” ¶ [0075]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. as modified by Fujimori et al. with thickness of each of the second pads is greater than a thickness of each of the first pads of Huang et al. in order to provide bridging-resistant bump structures that limits a bump shift range, and avoids bump bridging that leads to unintended electrical connection between bump structures (Huang et al. ¶ [0177]).
Regarding Claim 16, KIM et al. as modified by Huang et al. discloses the limitations of claim 15. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, further comprising semiconductor chips (“the first and second semiconductor chips 100 and 200” ¶ [0043]),
wherein the insulating layer 180, the first pads 160, and the second pads 320 are between the semiconductor chips 100 & 200 (“The bump structure 300 may be disposed between the first and second semiconductor chips 100 and 200 and may be electrically connected to the first and second semiconductor chips 100 and 200. The bump structure 300 may include a solder pattern 310 and a pillar pattern 320. The solder pattern 310 may be provided in the first hole 169 of the first redistribution pattern 160 and may cover the inner sidewall 160c of the first redistribution pattern 160. For example, the solder pattern 310 may be in contact with the inner sidewall 160c of the first redistribution pattern 160. The solder pattern 310 may also be provided in the first opening 189 of the first protective layer 180 and may be in contact with the inner sidewall 180c of the first protective layer 180.” ¶ [0043]).
Regarding Claim 17, KIM et al. as modified by Huang et al. discloses the limitations of claim 16. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein each of the first pads 160 comprises copper or a copper alloy (“The first redistribution pattern 160 may include a seed pattern 161 and a conductive pattern 162. For example, the seed pattern 161 may include at least one of titanium or copper. The bottom surface of the first redistribution pattern 160 may mean a bottom surface of the seed pattern 161. The conductive pattern 162 may be disposed on the seed pattern 161, and may be in contact with a top surface of the seed pattern 161. The conductive pattern 162 may include a metal such as copper, nickel, or any alloy thereof.” ¶ [0037]),
wherein each of the second pads comprises copper or a copper alloy (“The pillar pattern 320 may include a conductive material such as copper.” ¶ [0044]), and
wherein the solders are in direct contact with the copper or copper alloy of the first pads (“the solder pattern 310 may be in good contact with the inner sidewall 160c of the first redistribution pattern 160” ¶ [0046]).
However, KIM et al. does not disclose, the solders are in direct contact with the copper or copper alloy of the second pads.
In the similar field of endeavor of semiconductor package Huang et al. Figs. 3A-3H and 7A-7B discloses the solders (“solder material portions 40” ¶ [0164]) are in direct contact (Fig. 7A shows 40 in direct contact with 36 of 30) with the copper or copper alloy of the second pads (“each second metallic bump structure 30 may comprise a first copper plate portion 32, a nickel plate portion 34, and a second copper plate portion 36” ¶ [0165]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. as modified by Fujimori et al. with the solders are in direct contact with the copper or copper alloy of the second pads of Huang et al. in order to provide bridging-resistant bump structures that limits a bump shift range, and avoids bump bridging that leads to unintended electrical connection between bump structures (Huang et al. ¶ [0177]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over KIM; NAMHOON (US 20220013501 A1) “KIM et al.” in view of Fujimori, Joji (US 20040046252 A1) “Fujimori et al.” further in view of Hirano; Koichi (US 20080142966 A1) “Hirano et al.”.
Regarding Independent Claim 18, KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B discloses a semiconductor package (“a semiconductor package” ¶ [0025]) comprising:
semiconductor chips (“the first and second semiconductor chips 100 and 200” ¶ [0043]);
an insulating layer (“a first protective layer 180” ¶ [0028]) between the semiconductor chips 100 and 200;
first pads (“a first redistribution pattern 160” ¶ [0028]) respectively surrounded by the insulating layer 180;
solders 310 surrounded by the insulating layer 180 (“The solder pattern 310 may also be provided in the first opening 189 of the first protective layer 180 and may be in contact with the inner sidewall 180c of the first protective layer 180.” ¶ [0043]),
an underfill between the semiconductor chips (“A second underfill layer 420 may be provided in a second gap region between the top surface of the first semiconductor chip 100 and the bottom surface of the second semiconductor chip 200” ¶ [0050]); and
second pads (“a pillar pattern 320” ¶ [0043]) surrounded by the underfill 420 and compressing (“a bottom surface 320b of the pillar pattern 320 may be in contact with the solder pattern 310. … At least a portion of the pillar pattern 320 may be provided in the first opening 189. For example, the bottom surface 320b of the pillar pattern 320 may be disposed at a lower level than the top surface 180a of the first protective layer 180” ¶ [0044]) the epoxy solders 310 on the first pads 160.
However, KIM et al. does not disclose epoxy solders surrounding each of the first pads, the epoxy solders comprising solder particles and an epoxy resin;
In the similar field of endeavor of semiconductor package Fujimori et al. Figs. 2-6 discloses epoxy solders surrounding each of the first pads (“openings B in the film-like solder resist 81 on the electrode pads 71 as shown in FIG. 3 where a width W2 is greater than a width W1. The width W2 of the opening B may be about 1.3 to 3.0 times as large as the width W1 of the electrode pad 71, for example” ¶ [0082]), the epoxy solders comprising solder particles and an epoxy resin (“solder paste 90, which is a mixture of powder or granular solder and thermosetting resin 171” ¶ [0083]; “An epoxy-type resin may be used as the thermosetting resin 171. The ratio of the solder to the thermosetting resin 171 in the solder paste 90 may be adjusted within a range of 70-92 wt % of solder and 8-25 wt % of thermosetting resin 171.” ¶ [0084])
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. including the margin layer of Fujimori et al. in order to form the cured resin member that supports the solder ball. Since a single heating process suffices to form the solder ball and the cured resin member simultaneously, manufacturing steps are simplified. Further, the cured resin member is placed between the solder ball and the electrode pad, so that it serves to reinforce the strength of connection between the solder ball and the electrode pad. (Fujimori et al. ¶ [0021]).
However, Fujimori et al. does not explicitly disclose, wherein solder particles.
In the similar field of endeavor of semiconductor package Hirano et al. Figs. 2A(a)-2A(d) discloses solder particles (“The moving metal particles 1,1' are allowed to self-assemble into a region between each electrode 7 of the semiconductor chip 8 and each electrode 5 of the circuit substrate 6 as shown in FIG. 2A(c) due to high wettability of the electrodes 5 and 7” ¶ [0138]; “A metal component constituting the metal particles 1,1' melts as the temperature rises. The melted metal component agglomerates and grows so as to interconnect each electrode 7 of the semiconductor chip 8 and each electrode 5 of the circuit substrate 6. The melting of the metal component causes the melting of the metal layer 2 of the metal particle 1. Thus, the first component 3a (dicyandiamide) that has been contained in the metal particles 1 is released into the second component 3b (bisphenol A type epoxy resin), which leads to a contact of the first component 3a and the second component 3b. This contact initiates a curing reaction between the first component 3a and the second component 3b, and thereby a thermoset resin 3c is formed. The formation of the thermoset resin 3c causes a viscosity rise of the composition 4. This means that the viscosity of the composition 4 is kept low while the metal particles 1,1' are moving since the curing reaction is not yet initiated during the starting phase of the heating.” ¶ [0139]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. as modified by Fujimori et al. with the solder particles of Hirano et al. in order to provide a composition that can solve a problem attributable to the viscosity increase. Also, another object of the present invention is to provide a satisfactory flip chip mounting process and a satisfactory bump-forming process in terms of a prevented short-circuit and thus in terms of a connecting reliability (Hirano et al. ¶ [0018]) and to reduce a amount of the residual metal particles that are left outside of electrodes or outside of the region between the opposed electrodes, which will lead to a prevention of the short-circuit. As a result, an excellent connecting reliability between the opposed electrodes is achieved (Hirano et al. ¶ [0067]).
Regarding Claim 19, KIM et al. as modified by Fujimori et al. and Hirano et al. discloses limitations of claim 18. However, KIM et al. does not disclose, wherein each of the epoxy solders comprises an in-between region between the first pads and the second pads, and
a margin region surrounding the in-between region, and
wherein a density of the solder particles in the in-between region is higher than a density of the solder particles in the margin region.
In the similar field of endeavor of semiconductor package Hirano et al. Figs. 2A(a)-2A(d) discloses wherein each of the epoxy solders (“metal particles 1,1' can be referred to also as "solder particles”” ¶ [0117]) comprises an in-between region (region between the opposed electrodes where the connection 10 in Fig. 2A(d)) between the first pads 5 and the second pads 7, and
a margin region (“thermoset resin 3c” ¶ [0139]) surrounding the in-between region (Fig. 2A(d) shows 3c surrounding 10).
wherein a density of the solder particles in the in-between region is higher than a density of the solder particles in the margin region (“a satisfactory convection effect is provided so that the self-assembly of the metal particles is achieved wherein the metal particles are allowed to move onto the electrodes or into a region between the opposed electrodes.” ¶ [0066]; “the metal particles are allowed to efficiently self-assemble onto the electrodes or into a region between the opposed electrodes. It is thus possible to reduce a amount of the residual metal particles that are left outside of electrodes or outside of the region between the opposed electrodes” ¶ [0067])
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor package of KIM et al. as modified by Fujimori et al. with the epoxy solders comprises an in-between region between the first pads and the second pads and the margin of Hirano et al. in order to provide a composition that can solve a problem attributable to the viscosity increase. Also, another object of the present invention is to provide a satisfactory flip chip mounting process and a satisfactory bump-forming process in terms of a prevented short-circuit and thus in terms of a connecting reliability (Hirano et al. ¶ [0018]) and to reduce a amount of the residual metal particles that are left outside of electrodes or outside of the region between the opposed electrodes, which will lead to a prevention of the short-circuit. As a result, an excellent connecting reliability between the opposed electrodes is achieved (Hirano et al. ¶ [0067]).
Regarding Claim 20, KIM et al. as modified by Fujimori et al., Hirano et al. and Sawada et al. disclose limitations of claim 19. KIM et al. Figs. 1A-1D, 2A-2D, 3, 4A-4B further discloses, wherein the underfill 420 is on an upper surface of the insulating layer (“the second underfill layer 420 disposed on the top surface 180a of the first protective layer 180” ¶ [0051]), and
wherein a level of lower surfaces of the second pads 320 is lower than a level of the upper surface of the insulating layer (“the bottom surface 320b of the pillar pattern 320 may be disposed at a lower level than the top surface 180a of the first protective layer 180.” ¶ [0044]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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