Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 06/24/2026 have been fully considered but are respectfully not deemed to be persuasive.
On page 2 of the remarks, it is alleged that Friedman does not disclose the claim limitation, “flipping one or more of the hard bits corresponding to the bit positions of the identified weak-bits and a determination as to whether a packet after flipping the one or more hard bits passes the CRC” of claim 1. In response, it is noted that flipping one of the weak-bits and the sequential bit occurs until a stop condition, wherein a stop condition includes a modified bit stream passes the CRC in Friedman par. 0049. It is unclear from the statement on page 2 of the remarks: “nowhere in Friedman discloses the flipping one or more of the hard bits corresponding to the bit positions of the identified weak-bits and a determination as to whether a packet after flipping the one or more hard bits passes the CRC”, as to what applicant considers as “hard bits” in Friedman.
Furthermore, in the examiner’s opinion, this claim would have been obvious according to rationale B (simple substitution), as expressed in the Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103 in View of the Supreme Court Decision in KSR International Co. v. Teleflex Inc., as published at 72 Federal Register 57526 et seq. (10/10/2007).
The scope and content of the prior art includes, in the Friedman et al. disclosure, a description of the method comprising every limitation in claim 1 except identifying hypothesized bit error positions, flipping hard bits corresponding to the hypothesized bit error positions, and determining if a packet passes the CRC after flipping the hard bits. Note par. 0026, 0049, and 0103-0104 in Friedman et al. The difference between the prior art method disclosed by Friedman et al. and the claim 1 method is that the claim requires simply substituting the hard bits corresponding to hypothesized bit error positions for Friedman et al.’s weak-bit indices corresponding to positions in the bit stream with low confidence – a predictable substitution well understood by those of skill in the art. Due to the reasons provided, the rejection is maintained.
On page 3 of the remarks, it is further alleged that “Independent claims 11 and 20 are also patentable over Friedman, for at least the same reasons given above in connection with claim 1. Due to the reasons provided above, the rejections are maintained.
On page 3 of the remarks, it is further alleged that “Given that the rest of the claims depend from one of the above independent claims, at least for the reasons similar to those discussed above, it is respectfully submitted that the rest of the claims are patentable over the cited reference”. Due to the reasons provided above, the rejections are maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Friedman et al. (US Pat. Pub. 20220200726; hereinafter referred to as Friedman).
As per claims 1 and 11:
Friedman teaches A method and a receiver, comprising:
a wireless interface configured to receive one or more packets (Friedman par. 0103-0104, antennas 910 and transceiver 920 arranged to receive signals);
a processing device configured to perform operations (Friedman par. 0103-0104, processing circuitry 950 configured to perform various operations) comprising:
receive a packet to generate soft bits and corresponding hard bits for bits of the packet, the hard bits representing a binary decision for each of the bits based on the corresponding soft bits (Friedman par. 0026, receive packet by soft decision demodulation into a bit stream and determine soft information indicating a likelihood of being erroneous for bits in the bit stream);
determine if the hard bits of the packet pass a cyclic redundancy check (CRC) (Friedman par. 0049, determine if weak-bits of a bit stream pass a CRC);
Friedman does not explicitly disclose to identify one or more hypothesized bit error positions for the bits of the packet based on the soft bits in responsive to determining that the hard bits of the packet fail the CRC; flip one or more of the hard bits corresponding to the one or more hypothesized bit error positions; and determine if the packet after said flip of the hard bits passes the CRC. However, Friedman teaches that his invention (his Bluetooth receiver and electronic device for said Bluetooth receiver) is related to the field of transmission technologies. It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to realize Friedman’s Bluetooth receiver and electronic device and method for said Bluetooth receiver would have related to identify one or more hypothesized bit error positions for the bits of the packet based on the soft bits in responsive to determining that the hard bits of the packet fail the CRC; flip one or more of the hard bits corresponding to the one or more hypothesized bit error positions; and determine if the packet after said flip of the hard bits passes the CRC because Friedman teaches to identify a number of weak-bits based on the soft information and to sort the weak-bits in an order of the likelihood of being erroneous, including weak-bit indices {3,19,106,432,433,519}, which a person of ordinary skill in the art would recognize as hypothesized bit error positions (Friedman par. 0026 and par. 0064). Friedman further teaches to identify a number of weak-bits based on the soft information and to sort the weak-bits in an order of the likelihood of being erroneous (Friedman par. 0027 and par. 0057).
As per claim 20:
Friedman teaches A communication device, comprising:
one or more antennas configured to receive a packet (Friedman Par. 0103-0104, antennas 910 arranged to receive signals);
a demodulator connected to the one or more antennas (Friedman Par. 0103, PHYC circuitry 930 includes circuitry for modulation/demodulation connected via antenna 910), the demodulator configured to:
generate soft bits and corresponding hard bits for bits of the packet, the hard bits representing a binary decision for each of the bits based on the corresponding soft bits (Friedman par. 0073, demodulate the receive packet by sofit decision demodulation into a bit stream and determine soft information indicating the respective likelihood of being erroneous for bits in the bit stream);
and a processing device (Friedman par. 0103, processing circuitry 950) configured to:
determine if the hard bits of the packet pass a cyclic redundancy check (CRC) (Friedman par. 0049, determine if weak-bits of a bit stream pass a CRC);
Friedman does not explicitly disclose to identify one or more hypothesized bit error positions for the bits of the packet based on the soft bits in responsive to determining that the hard bits of the packet fail the CRC; flip one or more of the hard bits corresponding to the one or more hypothesized bit error positions; and determine if the packet after said flip of the hard bits passes the CRC. However, Friedman teaches that his invention (his Bluetooth receiver and electronic device for said Bluetooth receiver) is related to the field of transmission technologies. It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to realize Friedman’s Bluetooth receiver and electronic device and method for said Bluetooth receiver would have related to identify one or more hypothesized bit error positions for the bits of the packet based on the soft bits in responsive to determining that the hard bits of the packet fail the CRC; flip one or more of the hard bits corresponding to the one or more hypothesized bit error positions; and determine if the packet after said flip of the hard bits passes the CRC because Friedman teaches to identify a number of weak-bits based on the soft information and to sort the weak-bits in an order of the likelihood of being erroneous, including weak-bit indices {3,19,106,432,433,519}, which a person of ordinary skill in the art would recognize as hypothesized bit error positions (Friedman par. 0026 and par. 0064). Friedman further teaches to identify a number of weak-bits based on the soft information and to sort the weak-bits in an order of the likelihood of being erroneous (Friedman par. 0027 and par. 0057).
As per claims 2 and 12:
Friedman further teaches the method of claim 1 and the receiver of claim 11, wherein the soft bits represent metrics to indicate a probability of a wrong decision for a corresponding one of the hard bits (Friedman par. 0044, soft metric that indicates weak bits) and wherein the hypothesized bit error positions indicate the hard bits representing one or more highest probabilities of a wrong binary decision in the packet (Friedman par. 0064, weak-bit indices of the packet are a list of values or error positions).
As per claims 3 and 13:
Friedman further teaches the method of claim 2 and the receiver of claim 12, wherein the processing device configured to flip one or more of the hard bits comprises the processing device configured to: flip a first bit of the hard bits indicated by the hypothesized bit error positions as representing a highest probability of a wrong binary decision; and flip a second bit of the hard bits immediately following the first bit (Friedman par. 0049-0050, flip a first bit and a sequential bit in a bit stream of an i-th iteration. Please note weak-bits are flipped in the order of the likelihood of being erroneous as stated in Friedman par. 0052).
As per claims 4 and 14:
Friedman further teaches the method of claim 3 and the receiver of claim 13 wherein the processing device configured to determine if the packet after said flip of the hard bits passes the CRC comprises the processing device configured to: determine that the packet after said flip of the first bit and the second bit still fails to pass the CRC (Friedman par. 0049, determine the bit stream and a modified bit stream created after flipping fail a CRC); un-flip the first bit and the second bit back to their binary decisions as originally generated; flip a third bit of the hard bits indicated by the hypothesized bit error positions as representing a second highest probability of a wrong binary decision; and flip a fourth bit of the hard bits immediately following the third bit (Friedman par. 0050, flip one weak-bit and a sequential bit with an unused permutation of weak-bits. Please note examiner interprets this as un-flipping previous permutations to try new permutations).
As per claims 5 and 15:
Friedman further teaches the method of claim 3 and the receiver of claim 13, wherein the processing device configured to determine if the packet after said flip of the hard bits passes the CRC comprises the processing device configured to: determine that the packet after said flip of the first bit and the second bit still fails to pass the CRC (Friedman par. 0049, determine the bit stream and a modified bit stream created after flipping fail a CRC); un-flip the second bit back to its binary decision as originally generated; and determine if the packet after said flip of only the first bit passes the CRC (Friedman par. 0054 CRC is performed for all possible ways to fix an erroneous bit in the bit stream. Please note examiner interprets this as inherently including single-bit flips).
As per claims 6 and 16:
Friedman further teaches the method of claim 2 and the receiver of claim 12, wherein the processing device configured to flip one or more of the hard bits comprises the processing device configured to: repeatedly flip two consecutive bits of the hard bits as originally generated (Friedman par. 0056, iterative flipping of weak-bit and sequential bit in each iteration), wherein a first bit of the two consecutive bits is indicated by the hypothesized bit error positions as representing a highest probability of a wrong binary decision in a descending order of probabilities (Friedman par. 0052, bits are flipped iteratively in the order of the likelihood of being erroneous), until the packet with said flip of the two consecutive bits passes the CRC or until the hard bits indicated by each of the hypothesized bit error position are flipped without the packet with said flip of the two consecutive bits passing the CRC (Friedman par. 0053, CRC is performed until one modified bit stream is found, which passes the CRC).
As per claims 7 and 17:
Friedman further teaches the method of claim 2 and the receiver of claim 12, wherein the processing device configured to flip one or more of the hard bits comprises the processing device configured to: repeatedly flip a single bit of the hard bits as originally generated (Friedman par. 0056, iterative flipping of weak-bit and sequential bit in each iteration), wherein the single bit is indicated by the hypothesized bit error positions as representing a highest probabilities of a wrong binary decision in a descending order of probabilities (Friedman par. 0052, bits are flipped iteratively in the order of the likelihood of being erroneous), until the packet with the single bit flipped passes the CRC or until the hard bits indicated by each of the hypothesized bit error position are flipped without the packet with the single bit flipped passing the CRC (Friedman par. 0054 CRC is performed for all possible ways to fix an erroneous bit in the bit stream. Please note examiner interprets this as inherently including single-bit flips).
As per claims 8 and 18:
Friedman further teaches the method of claim 2 and the receiver of claim 12, wherein the processing device configured to flip one or more of the hard bits comprises the processing device configured to: flip a first bit of the hard bits indicated by the hypothesized bit error positions as representing a highest probability of a wrong binary decision; and flip a second bit of the hard bits indicated by the hypothesized bit error positions as representing a next highest probability of a wrong binary decision (Friedman par. 0049-0050, flip a first bit and a sequential bit in a bit stream of an i-th iteration. Please note weak-bits are flipped in the order of the likelihood of being erroneous as stated in Friedman par. 0052).
As per claims 9 and 19:
Friedman further teaches the method of claim 1 and the receiver of claim 11, wherein the processing device configured to determine if the packet passes the CRC comprises the processing device configured to: determine an error syndrome of the packet, wherein the error syndrome of the packet indicates that the packet has at least one error bit in the hard bits (Friedman par. 0059, generate a lookup table with syndromes for the bit stream. Please note syndromes are generated for weak-bit indices according to a soft-metric as stated in Friedman par. 0060-0065); generate one or more error syndromes corresponding to one or more error bits at the hypothesized bit error positions (Friedman par. 0059, run CRC on the syndromes, wherein the CRC is passed if it is passed for one of the modified lookup tables); sum in an exclusive-or manner the error syndromes corresponding to the one or more error bits (Friedman par. 0061, XOR summation is used on the bit stream syndrome to the relevant weak-bits syndromes according to weak-bit indices); and determining that the error syndrome of the packet equals the sum of the error syndromes corresponding to the one or more error bits (Friedman par. 0067-0068, test all combinations until CRC passes for exactly one combination); and flip one or more of the hard bits indicated by the hypothesized bit error positions (Friedman par. 0068, after one combination is found, the relevant bits are flipped).
As per claim 10:
Friedman further teaches the method of claim 1, wherein the packet comprises a Bluetooth Low Energy (BLE) packet (Friedman par. 0103, device is compliant with BLE) and wherein the soft bits comprise demodulated outputs of a BLE demodulator with decision feedback (Friedman par. 0073 soft decision demodulation to produce soft information. Please note decision feedback is shown in the error propagation in Gaussian Frequency Shift Keying as stated in par. 0064).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY A YANG whose telephone number is (703)756-1447. The examiner can normally be reached Monday - Friday 8:30 a.m. - 5:30 p.m. PST.
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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