DETAILED ACTION
This Final Action is responsive to communications: 07/23/2026.
In the response filed on 07/23/2026: no claims are amended; no claims are canceled; and no claims are added. Therefore, claims 1-14, 24, and 32-44 are pending in the application. Claims 1, 24, and 32 are independent.
Examiner Notes
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. see ADS for domestic priority details.
Claim Interpretation (invoking 35 U.S.C. §112(f))
5. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are applicable for claims 1-12, 24, 32-42.
For independent claims 1, 24, and 32:
1) “…first circuitry operable to access…” (claim 1, lines 4-6 functional limitation)
2) “…second circuitry operable to communicate…” (claim 1, lines 8-11 functional limitation)
3) “…logic circuitry operable to remap…” (claim 1, lines 12-16 functional limitation)
4) “…circuitry operable to communicate…” (claim 24, lines 5-6 functional limitation)
5) “…logic circuitry…operable to …identify …remap…” (claim 24, lines 7-14 functional limitation)
6) “…circuitry operable to communicate…” (claim 32, lines 5-6 functional limitation)
7) “…logic circuitry…operable to …detect …remap…” (claim 32, lines 7-14 functional limitation)
Similarly, for dependent claims 2-12, 24, 33-42:
8) dependent claims recite “…logic circuitry…operable to…” performs function (see claims 2-12, 33-42)
9) dependent claims recite “…circuitry operable to…” performs function (see claim 24)
The term "…operable to…" in each of the limitations (1) through (9) above is a generic placeholder that is not preceded by a structural modifier. For instance, none of the modifiers of “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” recites structure to perform the respective function(s).
Because the limitations above are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. However, the specification does not appear to set forth corresponding structure(s) for the recited functions in the
“…operable to…” limitations (1) through (9) above.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
6. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. — The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
7. Claims 1-14, 24, and 32-44 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1-12, 24, 32-42 fail to comply with the written description requirement, because the claims recite “…operable to…” limitations (1) through (9) above (see Claim Construction Section in this Office action) without having adequate support for corresponding structure(s) in the specification as these claim limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (see Claim Interpretation above as set forth in this Office action). As such, claims 1-12, 24, 32-42 recite functions that have no limits and covers every conceivable means for achieving the stated function in each of the limitations (1)-(9) above. That is, the Applicant fails to provide corresponding structure or acts that one of ordinary skill in the art would be able to determine its structural or functional equivalence. Without being able to determine this, how would one of ordinary skill in the art have the requisite notice that to infringe on the claim. Disclosure Fig. 1-Fig. 3 shows that “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” is a generic means which can be software, hardware, or a combination of hardware/ software. It is not clear what “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” encompasses and Fig 1-Fig. 7 fails to point to any “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” besides showing a black box. Spec para [0015], [0029], [0031], [0040] mentions “logic circuitry” but fails to describe any specific hardware, hooks associated with “logic circuitry” capable of performing recited functions. Spec para [0019], [0024], [0026], [0029] mentions “circuitry” but fails to describe any specific hardware, hooks associated with such capable of performing recited functions. Spec do not clearly identify “first circuitry” or “second circuitry”. Similarly, Fig 1-Fig. 7 fails to point to any “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry”. Therefore, each of “…operable to…” limitations (1) through (9) invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Accordingly, the disclosure is not commensurate with the scope of the claims.
All dependent claims inclusive of claims 1-14, 24, 32-44 are rejected under the same category.
For art rejection, “logic circuitry” and “circuitry” are interpreted as circuits part of memory controller and associated circuits.
Claim Rejections - 35 USC § 112
8. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
9. Claims 1-14, 24, and 32-44 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant(s) regard as their invention.
Claims 1-12, 24, 32-42 are indefinite, because it is unclear what corresponding structure(s) for performing the entire claimed function in the “…operable to…” limitations (1) through (9) (see Claim Interpretation section above) are as the written description fails to clearly disclose or link the corresponding structure to the entire claimed function. Each of “…operable to…” limitations (1) through (9) invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Disclosure Fig. 1-Fig. 3 shows that any “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” is a generic means which can be software, hardware, or a combination of hardware/ software. It is not clear what any “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” encompasses and Fig 1-Fig. 7 fails to point to any “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” besides showing generic diagrams. Spec para [0015], [0029], [0031], [0040] mentions “logic circuitry” but fails to describe any specific hardware, hooks associated with “logic circuitry” capable of performing recited functions. Spec para [0019], [0024], [0026], [0029] mentions “circuitry” but fails to describe any specific hardware, hooks associated with such capable of performing recited functions. Spec do not clearly identify “first circuitry” or “second circuitry”. For example, Fig. 3 points to the fact that “first circuitry” or “second circuitry” or “logic circuitry” or “circuitry” can be any of multiple circuits shown. Fig 1-Fig. 7 fails to point to “logic circuitry” or “circuitry”. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
All dependent claims inclusive of claims 1-14, 24, 32-44 are rejected under the same category.
For art rejection, “logic circuitry” and “circuitry” are interpreted as circuits part of memory controller and associated circuits.
The Applicant can amend:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
Or
The Applicant can affirmatively disclaim:
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01 (o) and 2181.
Claim Rejections - 35 USC § 102
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
12. Claims 1, 24, and 32 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niu et al. (US 11,151,006 B2).
Regarding independent claim 1, Niu teaches a system (Fig. 2C: 201 system. See Fig. 1- Fig. 5 for illustrated components and function), comprising:
a plurality of array dies stacked along a direction (Fig. 2C: 202 “HBM dies”. Col. 7, lines 10-12” “…stack of dies 202…”),
each array die (Fig. 2C: 202) comprising:
one or more memory arrays (Fig. 2C: 214: “HBM array”, 222 “spare storage”. See also Fig. 4A, Fig. 4B); and
one or more first interfaces (Fig. 2C: 212, 218 combined),
each first interface comprising first circuitry operable to access at least one corresponding memory array of the one or more memory arrays (col. 7, lines 30-37. Fig. 2C: 212, 218 for each HBM die); and
a logic die (Fig. 2C: 204) coupled with the plurality of array dies (Fig. 2C: 202),
the logic die (Fig. 2C: 204) comprising:
a plurality of second interfaces (Fig. 2C, Fig. 4A-Fig. 4B: TSVs/ conductors stemming from memory controller, connected to routing circuitry 420, 470 inputs-outputs. See col. 7, lines 33-37), each second interface comprising second circuitry (See Fig. 4A-Fig. 4B) operable to communicate access signaling with a respective first interface (Fig. 2C: 212, 218) of the plurality of array dies to access the at least one memory array corresponding to the respective first interface (col. 7, lines 30-37, Fig. 4A-Fig. 4B); and
logic circuitry (Fig. 2C: 232 memory controller circuitry) operable (operable to work in conjunction with 212, 218 in HBM die) to remap accessing of the plurality of array dies from one or more first memory arrays (Fig. 2C: 214. See also Fig. 4A-Fig. 4B) of the plurality of array dies using a first of the plurality of second interfaces (214 uses Fig. 4A-Fig. 4B: 414, 436, 476 routing circuit portions and associated connected TSVs/ conductors) to one or more second memory arrays (Fig. 2C: 222. See also Fig. 4A-Fig. 4B) of the plurality of array dies using a second of the plurality of second interfaces (222 uses Fig. 4A-Fig. 4B: 414, 434, 474 routing circuit portions and associated connected TSVs/conductors) based on an error associated with access of the one or more first memory arrays (Fig. 2C; col. 4, line 62-column 5, line 7; col. 7, lines 11-13, 59-63: "... RAS circuit 212 may include an address table 220 configured to store a list of memory addresses... that are associated with an error, and to map such a memory address error to a portion of the spare memory 222...". See also col. 10, lines 33-59; Fig. 4A; col. 12, lines 38-60; Fig. 4B; col. 13, lines 28-51).
Regarding independent claim 24, Niu teaches a system (Fig. 2C: 201 system. See Fig. 1- Fig. 5 for illustrated components and function), comprising:
a plurality of array dies stacked along a direction (Fig. 2C: 202 “HBM dies”. Col. 7, lines 10-12),
each array die (Fig. 2C: 202) comprising one or more memory arrays (Fig. 2C: 214: “HBM array”, 222 “spare storage”. See also Fig. 4A, Fig. 4B) and a non-volatile storage (Fig. 2C: 216 in context of col. 7, lines 24-25, col. 8, lines 51-53: ECC storage can be “flash” memory cells); and
a logic die (Fig. 2C: 204) coupled with the plurality of array dies (Fig. 2C: 202),
the logic die (Fig. 2C: 204) comprising:
a plurality of interfaces comprising circuitry (Fig. 4A-Fig. 4B: 414, 434, 436, 474, 476 routing circuit portions and associated conductors) operable to communicate access signaling to access memory arrays of the plurality of array dies (See col. 7, lines 30-37); and
logic circuitry (Fig. 2C: 232 memory controller, see Fig. 2C: 234 circuitry function) coupled with the plurality of interfaces (Fig. 2C: internal conductors) and operable to:
identify an error associated with one or more first memory arrays of the plurality of array dies based on accessing the non-volatile storage of one or more of the plurality of array dies (col. 7, lines 20-29: ECC engine 234 detects error using ECC storage 216); and
remap, based on identifying the error, accessing from the one or more first memory arrays (Fig. 2C: 214. See also Fig. 4A-Fig. 4B) using a first interface of the plurality of interfaces (Fig. 4A-Fig. 4B: 414, 436, 476 routing circuit portions and associated conductor circuitry) to one or more second memory arrays (Fig. 2C: 222. See also Fig. 4A-Fig. 4B) of the plurality of array dies using a second interface (Fig. 4A-Fig. 4B: 414, 434, 474 routing circuit portions and associated conductor circuitry) of the plurality of interfaces (Fig. 2C; col. 4, line 62-column 5, line 7; col. 7, lines 11-13, 59-63: "... RAS circuit 212 may include an address table 220 configured to store a list of memory addresses... that are associated with an error, and to map such a memory address error to a portion of the spare memory 222...". See also col. 10, lines 33-59; Fig. 4A; col. 12, lines 38-60; Fig. 4B; col. 13, lines 28-51).
Regarding independent claim 32, Niu teaches a system (Fig. 2C: 201 system. See Fig. 1- Fig. 5 for illustrated components and function), comprising:
a plurality of array dies stacked along a direction (Fig. 2C: 202 “HBM dies”. Col. 7, lines 10-12),
each array die (Fig. 2C: 202) comprising one or more memory arrays (Fig. 2C: 214: “HBM array”, 222 “spare storage”. See also Fig. 4A, Fig. 4B); and
logic die (Fig. 2C: 204) coupled with the plurality of array dies (Fig. 2C: 202),
the logic die (Fig. 2C: 204) comprising:
a plurality of interfaces (Fig. 2C, Fig. 4A, Fig. 4B: sets of TSVs/ conductors stemming from memory controller and connected routing circuitry 420, 470 inputs-outputs) comprising circuitry operable to communicate access signaling to access memory arrays of the plurality of array dies (See col. 7, lines 30-37); and
logic circuitry (Fig. 2C: 232 memory controller circuitry) coupled with the plurality of interfaces (Fig. 2C, Fig. 4A-Fig. 4B) and operable to:
detect an error (col. 7, lines 20-29: ECC engine 234 detects error) based on an attempt to access one or more first memory arrays (Fig. 2C: 214) of the plurality of array dies using a first interface (Fig. 4A-Fig. 4B: 414, 436, 476 and associated conductor circuitry) of the plurality of interfaces; and
remap, based on detecting the error, accessing of the plurality of array dies from the one or more first memory arrays (Fig. 2C: 214) using the first interface (Fig. 4A-Fig. 4B: 414, 436, 476 and associated conductor circuitry) to one or more second memory arrays of the plurality of array dies (Fig. 2C: 222. See also Fig. 4A-Fig. 4B) using a second interface of the plurality of interfaces (Fig. 4A-Fig. 4B: 414, 434, 474 and associated conductor circuitry).
No art rejection provided for dependent claims. See 112a, 112b rejections.
Response to Arguments
35 U.S.C. §112(a) rejections
A) Applicant argues that the 112a rejection of claims 1, 24, 32 are not proper because "first circuitry operable" and "circuitry operable" are described throughout spec with sufficient detail for the person having ordinary skill in the art to conclude that the inventor had possession of claims. See arguments description "...features of the "first circuitry operable to access" and the "circuitry operable to communicate" are described in view of the interface blocks discussed throughout the Specification as filed ( e.g., an interface block 245 of an array die and an interface block 220 of a logic die), the internal hardware of which is disclosed at least in Paragraphs [0060]-[0070] and FIG. 3. For example, FIG. 3 illustrates an example interface architecture in which an interface block may include a control interface 310 (including a receiver and one or more latches), one or more data interfaces 330, FIFO/SERDES circuitry 340, write/sense circuitry 350 (including sense amplifiers and drivers), synchronization/sequencer logic 360, timing circuitry 370, and an interface controller 320, each described as performing example access and communication functions. See, e.g., Specification ... [0060] - [0070]. The Specification further describes that an interface block 220 or an interface block 245 may include, for example, "signaling circuitry, multiplexing circuitry, processing circuitry, [and] controller circuitry," and describes write/read data-path circuitry that may communicate the recited access signaling…[0048], [0054]-[0056] (emphasis added)...." (Remarks, pages 11-12).
Applicant’s argument is not persuasive because applicant has not provided sufficient details. For independent claims 1, 24, and 32:
1) “…first circuitry operable to access…” (claim 1, lines 4-6 functional limitation. It is not clear)
2) “…second circuitry operable to communicate…” (claim 1, lines 8-11 functional limitation)
4) “…circuitry operable to communicate…” (claim 24, lines 5-6 functional limitation)
6) “…circuitry operable to communicate…” (claim 32, lines 5-6 functional limitation)
9) “…circuitry operable to…” performs function (see claim 24)
The term "…operable to…" in each of the limitations (1), (2), (4), (6), (9) above are a generic placeholder that are not preceded by a structural modifier. For instance,
a) none of the modifiers of “first circuitry” or “second circuitry” or “circuitry” recites structure to perform the respective function(s) in (1), (2), (4), (6), (9). Claims do not describe the structural modifiers/ hardware mentioned in arguments (see argument descriptions pages 11-12) which would overcome the rejection if such modifiers/ hardware are incorporated, captured and mapped in claim language properly.
b) spec paragraphs [0060]-[0070] and FIG. 3 fails to describe specific hardware architecture/ structure that is used to perform specific functions in (1), (2), (4), (6), (9). Rather refers to conceptual “blocks” or “interface blocks” that can be associated with the functions. There is not sufficient description of architecture/ structure of the blocks described that performs the function. Since “first circuitry” or “second circuitry” or “circuitry” can encompass any circuitry and their bounds are not described.
c) spec e.g., paragraphs [0060]-[0070] and FIG. 3 fails to correlate specific hardware architecture/ structure that perform specific functions in (1), (2), (4), (6), (9). Rather it appears that multiple major circuits or components (functional features of various components are vague) are associated with the functions.
d) spec e.g., paragraphs [0060]-[0070] and FIG. 3 fails to mechanism (discussion of how function is performed), or algorithm, functional step details that perform specific functions in (1), (2), (4), (6), (9).
B) Applicant argues that the 112a rejection of claims 1, 24, 32 are not proper because "logic circuitry” is described throughout spec with sufficient detail for the person having ordinary skill in the art to conclude that the inventor had possession of claims. See arguments described "...the "logic circuitry operable to remap," "to identify," and "to detect" may be described, for example, in view of a logic block 230 described throughout the Specification as filed. The logic block 230 may be coupled to each interface block 220 via respective buses 231 and may perform the recited remapping, for example, "using a multiplexing or mapping component between host interfaces 216 and interface blocks 220." See ... [0040] [0041], [0057], [0059]. The Specification also describes that the logic block 230 "may implement one or more aspects of a controller 215." … [0041]. The Specification further describes that such logic circuitry may be "implemented or performed with one or more processors, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, [or] discrete hardware components."... [0021], [0116], [0125], [0178]-[0179] (emphasis added). Additionally, the recited functions of "identify an error associated with one or more first memory arrays" may be understood, for example, in view of structure and acts such as accessing non-volatile storage 270/235 (e.g., fuses or anti-fuses) or detecting a failed attempted access using an interface block 220 ... [0049], [0082]-[0085], [0119]-[0120]..." (Remarks, pages 11-12)
Applicant’s argument is not persuasive because applicant has not provided sufficient reasons for their arguments. For independent claims 1, 24, and 32:
3) “…logic circuitry operable to remap…” (claim 1, lines 12-16 functional limitation)
5) “…logic circuitry…operable to …identify …remap…” (claim 24, lines 7-14 functional limitation. It is not clear if “remap component”)
7) “…logic circuitry…operable to …detect …remap…” (claim 32, lines 7-14 functional limitation)
8) “…logic circuitry…operable to…” performs function (see claims 2-12, 33-42)
The term "…operable to…" in each of the limitations (3), (5), (7), (8) above are a generic placeholder that are not preceded by a structural modifier. For instance,
a) none of the modifiers of “logic circuitry” recite structure to perform the respective function(s) in (3), (5), (7), (8). Claims do not describe the structural modifiers/ hardware mentioned in arguments (see argument descriptions pages 11-12) which would overcome the rejection if such modifiers/ hardware are captured and mapped in claim language properly.
b) spec paragraphs e.g., [0021], [0116], [0125], [0178]-[0179] and Fig. 2, FIG. 3 fails to describe specific hardware architecture/ structure that is used to perform specific functions in (3), (5), (7), (8). Rather refers to conceptual block “logic circuitry” that can be associated with the functions. There is not sufficient description of architecture/ structure of the blocks described that performs the function.
c) spec e.g., [0021], [0116], [0125], [0178]-[0179] and Fig. 2, FIG. 3 fails to correlate specific hardware architecture/ structure that perform specific functions in (3), (5), (7), (8). Rather it appears that multiple major circuits or components (functional features of various components are vague) are associated with the functions.
d) spec e.g., [0049], [0082]-[0085], [0119]-[0120], and Figures fail to describe mechanism (discussion of how function is performed), or algorithm, functional step details that perform specific functions in in (3), (5), (7), (8).
35 U.S.C. §112(b) rejections
A) Applicant argues that the 35 U.S.C. 112(b) rejection of claims 1, 24, 32 are not proper because the structures that perform the recited " ... operable to ... " functions are described throughout the Specification as filed in such a manner that a person having ordinary skill in the art would understand what is claimed. See descriptions “…A claim term, however, may be definite even where it may encompass more than one structure. The question under 35 U.S.C. § 112(b) is whether a person having ordinary skill in the art would understand the scope of the claim with reasonable certainty when the claim is read in light of the Specification, and a claim term may be definite even where it may be understood to have a sufficiently definite meaning as the name for a broad class of structures. See MPEP § 218l(A). For example, "[i]f persons of ordinary skill in the art reading the specification understand the term to have a sufficiently definite meaning as the name for the structure that performs the function, even when the term covers a broad class of structures or identifies the structures by their function," then "35 U.S.C. 112(f) will not apply." ... a person having ordinary skill in the art would understand the recited "first circuitry," "second circuitry," "circuitry," and "logic circuitry" as the name for a class of hardware structures that may perform the recited functions…” (Remarks, pages 13-14).
Applicant’s arguments are not persuasive because applicant has not provided sufficient reasons for their arguments. Claim limitations (1)-(9) described in rejection invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The disclosure is devoid of any structure that performs the function in the claim. The examiner notes that the corresponding structure in specification for “first circuitry” or “second circuitry” or “circuitry” or "logic circuitry" are conceptual diagrams/ circuitry as disclosed in specification because there is no discussion, in the specification, of what accomplishes the generation of functions (1)-(9). Therefore, the claims are indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. MPEP 2181 II. B discloses "merely referencing a specialized computer ( e.g., a "bank computer"), some undefined component of a computer system ( e.g., "access control manager"), "logic," "code," or elements that are essentially a black box designed to perform the recited function, will not be sufficient because there must be some explanation of how the computer or the computer component performs the claimed function. Blackboard, Inc. v. Desire2Learn, Inc., 574 F.3d 1371, 1383-85, 91 USPQ2d 1481, 1491-93 (Fed. Cir. 2009); Net Money IN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1366-67, 88 USPQ2d 1751, 1756-57 (Fed. Cir. 2008); Rodriguez, 92 USPQ2d at 1405-06."
B) Applicant argues that the 35 U.S.C. 112(b) rejection of claims 1, 24, 32 are not proper because: “…he Specification describes example structures that may correspond to such functions such as the interface blocks 220/245 and their constituent hardware (e.g., control interface 310, data interface(s) 330, FIFO/SERDES 340, write/sense circuitry 350, synchronization/sequencer logic 360, timing circuitry 370, and interface controller 320 of FIG. 3), and the logic block 230 and its constituent components shown in FIGs. 6 and 7, which may be implemented, for example, with processor-type hardware such as a controller 215 or one or more processors (e.g., a DSP, an ASIC, an FPGA, or discrete logic). See, e.g., Specification... [0021], [0040] - [0041], [0048], [0054]-[0057], [0059], [0060], [0070], [0106]-[0124], [0125], [0l78]-[0179]. Therefore, in view of these portions of the Specification as filed, a person having ordinary skill in the art would understand the structure that performs each of the recited " ... operable to ... "functions. Accordingly, for at least these reasons, a person having ordinary skill in the art would understand what is claimed by the " ... operable to ... " limitations, as recited in claims 1-14, 24, and 32-44..." (Remarks, pages 13-14).
Applicant’s arguments are not persuasive because applicant has not provided sufficient reasons for their arguments. See above
112(f) invocation:
Applicant argues that the 35 U.S.C. 112(f) invocation of claims 1, 24, 32 are not proper because applicant states “…this case, the claims recite sufficient structure to perform the claimed functions and therefore do not fall under the interpretation of 35 U.S.C. § 112(f). For example, "35 U.S.C. 112(f) ... will not apply if persons of ordinary skill in the art reading the specification understand the term to have a sufficiently definite meaning as the name for the structure that performs the function, even when the term covers a broad class of structures or identifies the structures by their function." MPEP § 218l(A) (emphasis added). In claims 1-12, 24, and 32-42, the claimed "circuitry," "first circuitry," "second circuitry," and "logic circuitry" would be understood by persons of ordinary skill in the art as a particular structure or a broad class of structures that may perform the claimed functions of "access …at least one corresponding memory array," "communicat…access signaling," and "remap[ping] accessing" as claimed. Indeed, Applicant submits "circuitry" is a term of art that connotes definite hardware structure to a person having ordinary skill in the art…” (Remarks, pages 14-16).
Applicant’s argument is not persuasive because applicant has not provided sufficient details. Many court cases supports the fact pattern of the instant application and the invocation of 112(f) is valid. For example, Magnolia Medical Technologies, Inc. v. American Medical Systems, LLC: The Federal Circuit reinforced that overcoming the presumption against § 112(f) requires reciting sufficient physical structure in the claim itself to perform the entire function, evaluated through the lens of the specification.
Applicant argues that the 35 U.S.C. 112(f) invocation of claims 1, 24, 32 are not proper because “…according to the MPEP, "[t]he term is not required to denote a specific structure or a precise physical structure to avoid the application of 35 U.S.C. 112(F)." MPEP § 2181(A) (citing Inventio AG v. Thyssenkrupp Elevator Americas Corp., 649 F.3d 1350 (Fed. Cir. 2011) (holding that the claim terms "modernizing device" and "computing unit," when read in light of the specification connoted sufficient, definite structure to one of skill in the art to preclude application of 35 U.S.C. 112, sixth paragraph)) (emphasis added). Thus, under at least the interpretation of Inventio, the claimed "circuitry," "first circuitry," "second circuitry," and "logic circuitry" should not be interpreted under 112(f) for at least the reasons that the claim language itself, the written description, and the figures connote sufficient structure to perform the claimed function….” (Remarks, pages 14-16).
Applicant’s argument is not persuasive because the fact pattern of the case law used here is different from our instant application and applicant has not provided sufficient details. For example, for invoking § 112(f), see Williamson v. Citrix Online, LLC, 792 F.3d 1339 (Fed. Cir. 2015) where the Federal Circuit sat en banc to lower the threshold for invoking means-plus-function treatment, holding that a failure to use the word "means" still triggers § 112(f) if the claim term lacks sufficiently definite structure and instead recites function.
Prior art rejections:
Applicant's arguments filed 07/23/2026 have been fully considered but they are not persuasive.
Applicant argues that the anticipation rejection of claim 1 over Niu et al. (US 11,151,006 B2) is not proper because Niu does not teach -
“…logic circuitry operable to remap accessing of the plurality of array dies from one or more first memory arrays of the plurality of array dies using a first of the plurality of second interfaces to one or more second memory arrays of the plurality of array dies using a second of the plurality of second interfaces based on an error associated with access of the one or more first memory arrays…” (1). (Remarks, pages 16-19).
Anticipation rejection of claims 24, 32 are not proper for the same/ similar reason.
1) Applicant argue that Niu does not teach (1) because “…merely mapping memory addresses to a spare memory, as described by Niu, is not the same” as claimed function (1). (Remarks page 18)
Applicant’s arguments are not persuasive because applicant has not provided sufficient reasons for their arguments. Niu teaches logic circuitry (Fig. 2C: 232 memory controller circuitry) operable (operable to work in conjunction with 212, 218 in HBM die) to remap accessing of the plurality of array dies from one or more first memory arrays (Fig. 2C: 214. See also Fig. 4A-Fig. 4B) of the plurality of array dies using a first of the plurality of second interfaces (214 uses Fig. 4A-Fig. 4B: 414, 436, 476 routing circuit portions and associated connected TSVs/ conductors) to one or more second memory arrays (Fig. 2C: 222. See also Fig. 4A-Fig. 4B) of the plurality of array dies using a second of the plurality of second interfaces (222 uses Fig. 4A-Fig. 4B: 414, 434, 474 routing circuit portions and associated connected TSVs/conductors) based on an error associated with access of the one or more first memory arrays (Fig. 2C; col. 4, line 62-column 5, line 7; col. 7, lines 11-13, 59-63: "... RAS circuit 212 may include an address table 220 configured to store a list of memory addresses... that are associated with an error, and to map such a memory address error to a portion of the spare memory 222...". See also col. 10, lines 33-59; Fig. 4A; col. 12, lines 38-60; Fig. 4B; col. 13, lines 28-51).
2) Applicant argue that Niu does not teach (1) because individual memory addresses are not the same as any such "array dies" as claimed (Remarks page 18)
Applicant’s arguments are not persuasive because applicant has not provided sufficient reasons for their arguments. The broad language in the claimed limitation encompasses the prior art teaching since Niu teaches -
(1) "The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory." (see abstract)
(2) “…circuit 212 may include an address table 220 configured to store a list of memory 60 addresses (within the memory cells 214) that are associated with an error, and to map such a memory address error to a portion of the spare memory 222…” (col 8)
(3) “…the HBM dies 202 may be capable of detecting an error in the memory cells 214 and remapping the bad memory addresses( es) to the spare storage 222, without the assistance of the host device 206 and processor 204…” (col 10)
(1), (2), (3) of Niu are encompassed by the broad claim language and broad claimed limitations.
3) Applicant argue that Niu does not teach (1) because routing data from memory cells on an HBM die to a RAS circuit on the HBM die, as described by Niu, is not the same as claimed (Remarks page 18-19). routing data to either memory cells or spare storage on an HBM die via a routing circuit, as described by Niu, is not the same as, and does not disclose (1) (Remarks page 19)
In response to applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., see above) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
4) Applicant argue that Niu does not teach (1) because routing circuit of Niu, nor any other portion of Niu, can be properly construed to be the same as "a plurality of second interfaces, each second interface comprising second circuitry operable to communicate access signaling with a respective first interface of the plurality of array dies" (Remarks page 19).
In response to applicant's argument that the references fail to show certain features of applicant’s invention, it is noted that the features upon which applicant relies (i.e., see above) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In general, applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made.
Prior Art Not relied upon
Patent Pub. No. 2015/0199246 to Miyazaki et al. and Patent Pub. No. 2014/0376320 to Loh et al. are applicable for all claims.
Eckel et al. (US 2024/0403165 A1): Fig. 2-Fig. 7 disclosure applicable for all claims. Eckel FIG. 2 illustrates an example of a system 200 (e.g., a semiconductor system, a system of coupled semiconductor dies) that supports information broadcast techniques for stacked memory architectures in accordance with examples as disclosed herein. The system 200 illustrates an example of a die 205 (e.g., a semiconductor die, a host die, a processor die, a logic die) that is coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, semiconductor dies, memory dies, array dies). Disclosed interface and interconnect structure are substantially identical to applicant’s disclosure.
Gupta Hyde et al. (US 2019/0051642 A1) is applicable for all claims. Gupta Hyde teaches Fig. 3 “multi-die package” structure constructed and mounted to the PCB which represents the limitation) a substrate (Fig. 3: 304 “substrate”); forming a first die (Fig. 3: 110/118 “memory die”, see para [0015]) on the substrate (Fig. 3: 304), stacking the second die over the first die comprises coupling the computational logic to the RAM of the first die (Fig. 3 in context of para [0016]: CPU and memory dies of 110, 112 are “…communicatively interconnected using TSVs…”).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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