DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 13-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (Okada et al., US 2024/0074214, cited in the IDS filed on 10/16/2024, hereinafter “Okada”).
Regarding claims 1, 13 and 20, Okada discloses a memory device, a method and a memory system (Figs. 1, 2 and 5, MD), comprising:
a first semiconductor structure (Fig. 5, CM) comprising a first memory array in a first array region (MP2), a second memory array (MP3) in a second array region, contact structures in a connection region (RHU) between the first array region and the second array region along a first direction (X direction), and word lines (Fig. 8, 110 and Fig. 18, WL(1)-WL(5)) coupled to memory cells in the first memory array and memory cells in the second memory array; and
a second semiconductor structure (CP) comprising row decoders,
wherein the first semiconductor structure and the second semiconductor structure are stacked together along a second direction perpendicular to the first direction (Figs. 5 and 8), and
wherein at least one part of the row decoders overlaps with at least one of the first memory array in the first array region or the second memory array in the second array region in a plan view perpendicular to the second direction (Fig. 12, RBD overlaps with MPx and Fig. 18, RBD overlaps memory region MCA).
Regarding claims 2 and 14, Okada discloses the memory device of claim 1 and the method of claim 13, wherein the second semiconductor structure further comprises string drivers (RRC), wherein a string driver of the string drivers is coupled to a corresponding word line through a contact structure in the connection region and coupled to a corresponding row decoder, and wherein at least a first part of the string drivers overlaps with the at least one of the first memory array in the first array region or the second memory array in the second array region in the plan view (Fig. 12, wherein RRC partially overlaps MPX, see also fig. 18, where RRC overlaps memory region MCA in one part).
Regarding claims 3 and 15, Okada discloses the memory device of claim 2 and the method of claim 14, wherein a second part of the string drivers overlaps with the contact structures in the connection region in the plan view (Fig. 18, where RRC overlaps contact region RHU in another part).
Regarding claims 4-6 and 16, Okada (Fig. 12) shows the memory device of claim 2 and the method of claim 14, wherein the row decoders are positioned adjacent to the string drivers along the first direction.
Allowable Subject Matter
Claims 7-12 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 7 and 17, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first semiconductor structure comprises N memory blocks numbered from 0 to N-1, wherein the first group of row decoders comprises a first row decoder coupled to first string drivers that are coupled to word lines in a first memory block associated with an odd number, and wherein the second group of row decoders comprises a second row decoder coupled to second string drivers that are coupled to word lines in a second memory block associated with an even number.” in combination with the other limitations thereof as is recited in the claim. Claims 8 and 18 depend on claim 7 and 17, respectively.
Regarding claims 9, 10 and 19, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the second semiconductor structure further comprises a first group of page buffers and a second group of page buffers, wherein the row decoders and the string drivers are positioned between the first group of page buffers and the second group of page buffers along the first direction, wherein the first semiconductor structure further comprises bit lines coupled to the memory cells in the first memory array, wherein the bit lines are coupled to corresponding page buffers of the first group of page buffers, and wherein at least one part of at least one of the bit lines is distanced from a corresponding page buffer along the first direction in the plan view.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 11, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the one of the bit lines is coupled to the corresponding page buffer through a first connection line in the first semiconductor structure and a second connection line in the second semiconductor structure, and wherein the second connection line comprises a first part overlapping with at least one of the row decoders or the string drivers, a second part overlapping with the first group of page buffers, and a third part connecting ends of the first part and the second part.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 12, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the first semiconductor structure comprises a first bonding layer comprising first conductive structures isolated by a first isolating material, wherein the second semiconductor structure comprises a second bonding layer comprising second conductive structures isolated by a second isolating material, and wherein the first semiconductor structure and the second semiconductor structure are bonded together with the first conductive structures being in contact with the second conductive structures.” in combination with the other limitations thereof as is recited in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 2020/0381037) discloses a 3-dimensional memory device.
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/HUAN HOANG/ Primary Examiner, Art Unit 2827
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