DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter (i.e.; “fourth sacrificial layer” and “connection region”). See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). For instance, the specification failed to explicitly teach what element represent the “fourth sacrificial layer”.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3-5, 12, 14-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter (i.e.; “fourth sacrificial layer” and “connection region”) which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 2021/0028186 A1 hereinafter referred to as “Lim”).
With respect to claim 1, Lim discloses, in Figs.1-19B, a method for manufacturing a semiconductor storage device, the method comprising: alternately stacking a plurality of first insulating layers (110) and a plurality of first sacrificial layers (120) on a first wiring layer (100) along a first direction/(x-direction); forming a second insulating layer (110l) on an uppermost layer of the plurality of first sacrificial layers (120) (see step of Fig.4B, Par.[0087]-[0090] wherein a plurality of the sacrificial layers 120a to 120k may be individually stacked on the substrate 100 and may be insulated from each other by the corresponding insulation interlayers 110a to 110l; see Par.[0030] wherein the substrate 100 may include a silicon substrate, a germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate and/or a germanium-on-insulator (GOI) substrate; the substrate 100 may include a composite substrate comprising a composition of Group III and Group V (i.e.; transition metals)); forming a first hole (UT) so as to pass through the plurality of first insulating layers (110), the plurality of first sacrificial layers (120), and the second insulating layer (110l) along the first direction/(x-direction) (see step of Fig.5B, Par.[0095]-[0098] wherein a dry etching process may be applied to the stack structure SS to a trench depth TD, until the sacrificial layer 120 and the insulation interlayer 110 may be sequentially removed downwards); etching side surfaces of the plurality of first sacrificial layers (120) through the first hole (UT) (see step of Fig.6B, Par.[0103]-[0109] wherein the horizontal recess HR may be adjacent with or may be joined to the upper trench UT and may extend in the second direction y and the third direction z; particularly, the etch stop sacrificial layer 128h′ may also be removed from the stack structure SS and the 8.sup.th sacrificial layer 128h may also be formed into a preliminary 8.sup.th sacrificial pattern 121h); filling the first hole (UT) with a second sacrificial layer (110h) (see step of Fig.6A, Par.[0103] wherein referring to FIGS. 6A and 6B, the preliminary 11.sup.th sacrificial pattern 121k, the preliminary 10.sup.th sacrificial pattern 121j, the preliminary 9.sup.th sacrificial pattern 121i and the etch stop sacrificial layer 120h′ may be partially removed from the stack structure SS in parallel with a surface of the substrate 100, thereby forming a plurality of horizontal recesses HR between the neighboring preliminary insulation interlayer patterns 111 and between the 8.sup.th insulation interlayer 110h and the preliminary 9.sup.th insulation interlayer pattern 111i); etching the second sacrificial layer (140) until the uppermost layer of the plurality of first sacrificial layers (140) is exposed to the first hole (UT, HR); causing a third sacrificial layer (142, 144) to be selectively grown on a side surface of the uppermost layer of the plurality of first sacrificial layers (120) (see steps of Figs.7A-7B, Par.[0106]-[0110] wherein referring to FIGS. 7A and 7B, a dummy channel stopper 140 may be formed in the horizontal recesses HR in such a configuration that the dummy channel stopper 140 may extend to the boundary area BA and be exposed to the upper trench UT; particularly, the stopper materials filling in the horizontal recess HR defined by the 8.sup.th preliminary sacrificial pattern 121h may be formed into a single bottom pattern 144 of the upper trench UT and the stopper materials filling in the horizontal recess HR defined by the 9.sup.th preliminary sacrificial pattern 121i, the 10.sup.th preliminary sacrificial pattern 121j and the 11.sup.th preliminary sacrificial pattern 121k may be formed into a plurality of side patterns 142 of the upper trench UT; the dummy channel stopper 140 may include the bottom pattern 144 and a plurality of the side patterns 142); removing the second sacrificial layer (110h) and forming a pillar (150, 250) including at least a semiconductor layer in the first hole (UT, HR) (see step of Fig.9B, Par.[0115]-[0123] wherein a single hole etching process may be conducted to the stack structure SS having the dummy channel stopper 140 and the filling body 150, to thereby form a plurality of channel holes CH in the cell block area C and a plurality of dummy holes DH across the boundary area BA and the block separation area BS; see Par.[0112]-[0116] wherein the filling layer may be partially removed by a planarization process until an upper surface of the preliminary 12.sup.th insulation interlayer pattern 111l may be exposed, thereby forming the filling body 150 in the upper trench UT; see Par.[0068] wherein the dummy channel structure 250 may have substantially the same structure as the channel structure 230, except that the dummy trap pattern 257 may include a triple pattern structure); removing the plurality of first sacrificial layers (120) and the third sacrificial layer (142, 144) (see Step of Fig.14B, Par.[0155]-[0161] wherein referring to FIGS. 14A to 14C, the residual stopper 140a and the sacrificial patterns 122 may be removed from the stack pattern SP to thereby form a plurality of gap spaces GS defined by the neighboring insulation interlayer patterns 112 that are substantially parallel with the substrate 100; For example, since the etch resistance of the residual stopper 140a and the sacrificial patterns 122 may be smaller than the insulation interlayer patterns 112 and may be exposed to the separation trench ST, the residual stopper 140a and the sacrificial patterns 122 may be removed from the stack pattern SP by an etch-back process using an aqueous phosphate solution or an aqueous sulfuric solution as an etchant); and forming a plurality of second wiring layers (330) in a region from which the plurality of first sacrificial layers (120) and the third sacrificial layer (140) have been removed (see step of Fig.16B, Par.[0165]-[0169] wherein the electrode patterns 300 may include a first gate line 310, a second gate line 320 and a third gate line 330 that may be sequentially stacked in the first direction x).
With respect to claim 2, Lim discloses, in Figs.1-19B, the method, wherein a side surface of the third sacrificial layer (140) facing the pillar and a side surface of an uppermost layer of the plurality of first insulating layers facing the pillar are substantially flat (see Figs.7B-12B).
With respect to claim 6, Lim discloses, in Figs.1-19B, the method, wherein forming the pillar (150, 250) includes forming an insulating film (252) on the third sacrificial layer (140) on the side surface of the uppermost layer of the plurality of first sacrificial layers (120) and a side surface of an uppermost layer of the plurality of first insulating layers (110) so as to form a substantially flat surface thereon (see Par.[0134] wherein thus, both of the charge trap pattern 232 and the preliminary dummy trap pattern 252a may include a tunnel insulation pattern T1 comprising an oxide and in contact with the hole spacer HS, a charge trap pattern T2 comprising a nitride and in contact with the tunnel insulation pattern T1, and a first blocking pattern T3 comprising an oxide and in contact with the charge trap pattern T2).
With respect to claim 7, Lim discloses, in Figs.1-19B, the method, wherein the insulating film is formed on a side surface of one of the first sacrificial layers (120) adjacent to the uppermost layer of the plurality of first insulating layers (110), and the insulating film (252) does not form a flat surface on said one of the first sacrificial layers and the side surface of the uppermost layer of the plurality of first insulating layers (see Figs.7B-12B).
With respect to claim 8, Lim discloses, in Figs.1-19B, the method, further comprising: forming a slit (ES) along the first direction through which the plurality of first sacrificial layers and the third sacrificial layer are removed (see Fig.14B, Par.[0158] wherein the gap spaces GS at the upper portion U of the stack pattern SP may be enlarged into enlarged spaces ES at the boundary area BA).
With respect to claim 9, Lim discloses, in Figs.1-19B, a method for manufacturing a semiconductor storage device, the method comprising: alternately stacking a plurality of first insulating layers (110) and a plurality of first sacrificial layers (120) on a first wiring layer (100) along a first direction/(x-direction); forming a second insulating layer (110l) on an uppermost layer of the plurality of first sacrificial layers (110) (see step of Fig.4B, Par.[0087]-[0090] wherein a plurality of the sacrificial layers 120a to 120k may be individually stacked on the substrate 100 and may be insulated from each other by the corresponding insulation interlayers 110a to 110l; see Par.[0030] wherein the substrate 100 may include a silicon substrate, a germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate and/or a germanium-on-insulator (GOI) substrate; the substrate 100 may include a composite substrate comprising a composition of Group III and Group V (i.e.; transition metals)); forming a first hole (UT) so as to pass through the plurality of first insulating layers (110), the plurality of first sacrificial layers (120), and the second insulating layer (110l) along the first direction (see step of Fig.6B, Par.[0103]-[0109] wherein the horizontal recess HR may be adjacent with or may be joined to the upper trench UT and may extend in the second direction y and the third direction z; particularly, the etch stop sacrificial layer 128h′ may also be removed from the stack structure SS and the 8.sup.th sacrificial layer 128h may also be formed into a preliminary 8.sup.th sacrificial pattern 121h); etching the plurality of first sacrificial layers (120) exposed to the first hole (UT) (see step of Fig.6B, Par.[0103]-[0109] wherein the horizontal recess HR may be adjacent with or may be joined to the upper trench UT and may extend in the second direction y and the third direction z; particularly, the etch stop sacrificial layer 128h′ may also be removed from the stack structure SS and the 8.sup.th sacrificial layer 128h may also be formed into a preliminary 8.sup.th sacrificial pattern 121h); filling the first hole with a second sacrificial layer (110h); etching the second sacrificial layer (110h) until at least an uppermost layer of the plurality of first insulating layers (110) is exposed to the first hole (UT); etching a side surface of the uppermost layer of the plurality of first insulating layers exposed to the hole (see step of Fig.9B, Par.[0115]-[0123] wherein a single hole etching process may be conducted to the stack structure SS having the dummy channel stopper 140 and the filling body 150, to thereby form a plurality of channel holes CH in the cell block area C and a plurality of dummy holes DH across the boundary area BA and the block separation area BS; see Par.[0112]-[0116] wherein the filling layer may be partially removed by a planarization process until an upper surface of the preliminary 12.sup.th insulation interlayer pattern 111l may be exposed, thereby forming the filling body 150 in the upper trench UT; see Par.[0068] wherein the dummy channel structure 250 may have substantially the same structure as the channel structure 230, except that the dummy trap pattern 257 may include a triple pattern structure); removing the second sacrificial layer (140), and then forming a first pillar (150, 250) including at least a semiconductor layer in the hole; removing the plurality of first sacrificial layers (see Step of Fig.14B, Par.[0155]-[0161] wherein referring to FIGS. 14A to 14C, the residual stopper 140a and the sacrificial patterns 122 may be removed from the stack pattern SP to thereby form a plurality of gap spaces GS defined by the neighboring insulation interlayer patterns 112 that are substantially parallel with the substrate 100; For example, since the etch resistance of the residual stopper 140a and the sacrificial patterns 122 may be smaller than the insulation interlayer patterns 112 and may be exposed to the separation trench ST, the residual stopper 140a and the sacrificial patterns 122 may be removed from the stack pattern SP by an etch-back process using an aqueous phosphate solution or an aqueous sulfuric solution as an etchant); and forming a plurality of second wiring layers in a region from which the plurality of first sacrificial layers have been removed (see step of Fig.16B, Par.[0165]-[0169] wherein the electrode patterns 300 may include a first gate line 310, a second gate line 320 and a third gate line 330 that may be sequentially stacked in the first direction x).
With respect to claim 10, Lim discloses, in Figs.1-19B, the method, wherein the plurality of first sacrificial layers (120) is etched such that the side surface of the uppermost layer of the plurality of first insulating layers (110) and a side surface of an uppermost layer of the plurality of first sacrificial layers are substantially flat (see Figs.7B-12B).
With respect to claim 11, Lim discloses, in Figs.1-19B, the method, further comprising: after filling the first hole with the second sacrificial layer and before removing the second sacrificial layer, forming a third sacrificial layer in the first hole and forming a concave in the third sacrificial layer such that a bottom portion of the concave is closer to the first wiring layer than a bottom surface of the second insulating layer in the first direction (see Fig.5B-7B wherein concave opening UT to concave bottom area of sacrificial layers are shown).
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho (US 2020/0402998 A1).
With respect to claim 13, Cho discloses, in Figs.1-23, a method for manufacturing a semiconductor storage device, the method comprising: alternately stacking a plurality of first insulating layers (110) and a plurality of first sacrificial layers (120b) on a first wiring layer along a first direction; alternately stacking a plurality of second insulating layers (110) and a plurality of second sacrificial layers (120a) on an uppermost layer of the plurality of first sacrificial layers (120b) along the first direction; forming a third insulating layer (130) on an uppermost layer of the plurality of second sacrificial layers (120b) (see step of Fig.3, Par.[0020]-[0021] wherein first to fourth insulating interlayers 130, 190, 290 and 310, a contact plug 300, and a bit line 320; the substrate 100 may include silicon, germanium, silicon-germanium or III-V (i.e.; transistor metals) compounds such as GaP, GaAs, GaSb, etc.; see Par.[0055] wherein the numbers of the insulation layer 110 and the sacrificial layer structure 120 are not limited thereto, and each of the insulation layer 110 and the sacrificial layer structure 120 may be formed in a greater number or a smaller number); forming a first hole (140) so as to pass through the plurality of first insulating layers (110), the plurality of first sacrificial layers (120b), the plurality of second insulating layers (120a), the plurality of second sacrificial layers (120a), and the third insulating layer (130) along the first direction (see step of Fig.4, Par.[0063]-[0065] wherein an etching process is subsequently performed using an etching mask to etch the first insulating interlayer 130, the insulation layers 110 and the sacrificial layers 120 thereunder, and a channel hole 140 extending through the first insulating interlayer 130, the insulation layers 110 and the sacrificial layers 120 may be formed to expose the upper surface of the substrate 100); etching side surfaces of the plurality of first sacrificial layers (120b) and the plurality of second sacrificial layers (120a) through the first hole (140) under a first etching condition in which a first etching rate for the plurality of first sacrificial layers (120b) is higher than a second etching rate for the plurality of second sacrificial layers (120a) (see step of Fig.5, Par.[0065]-[0068] wherein a sidewall of the second sacrificial layer 120b of each of the sacrificial layer structures 120 exposed by the channel hole 140 may be partially removed to form first recesses 150 (e.g., extending in the third direction); each of the first recesses 150 may be formed by only partially removing each of the second sacrificial layers 120b, and the recess may have a constant depth in the third direction; the first and second sacrificial layers 120a and 120b may have the etching selectivity with respect to each other, so that the first sacrificial layer 120a is not removed when the first recesses 150 are formed; see Par.[0060] wherein the first and second sacrificial layers 120a and 120b may include a silicon nitride, and the second sacrificial layer 120b may have a higher etching rate than the first sacrificial layer 120a for a specific etching solution or a specific etching gas); filling the first hole (140) with a third sacrificial layer (160) (see step of Fig.6, Par.[0069]-[0072] wherein the channel layer 160 may be formed to fill each of the first recesses 150, and a portion of an outer sidewall of the channel layer 160 adjacent to each of the second sacrificial layers 120b may protrude further than other portion of the outer sidewall thereof in a horizontal direction (e.g., in the third direction) to form a protrusion portion; the channel layer 160 may include polysilicon doped or undoped with impurities, or amorphous silicon); removing the third sacrificial layer (160) and forming a pillar (165) including at least a semiconductor layer in the first hole (140) (see step of Fig.7, Par.[0072]-[0077] wherein upper portions of each of the buried pattern 175 and the channel 165 may be removed to form a trench and a pad 180 may be formed to fill the trench); removing the plurality of first sacrificial layers (120b) and the plurality of second sacrificial layers (120a) (see step of Fig.8, Par.[0078]-[0082] wherein an opening 200 extending through the first and second insulating interlayers 130 and 190, the insulation layers 110, and the sacrificial layer structures 120 may then be formed to expose the upper surface of the substrate 100 by performing an etching process using an etching mask; the sacrificial pattern structures exposed by the opening 200 may be removed to form a gap 210 between the insulation patterns 115 of each level, and a portion of the outer sidewall of channel 165/160 may be exposed by the gap 210; the sacrificial pattern structures exposed by the opening 200 may be removed by a wet etching process using an etchant including phosphoric acid or sulfuric acid); and forming a plurality of second wiring layers (210) in a region from which the plurality of first sacrificial layers (120b) and the plurality of second sacrificial layers (120a) have been removed (see step of Fig.14, Par.[0109]-[0118] wherein a gate electrode layer may be subsequently formed on the second blocking layer 250 to efficiently fill a remaining portion of the gap 210).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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