DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3 and 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 depends directly from claim 2. Claim 2 requires: “reset switch is turned on.” Yet, claim(s) 3 and 4 seems to attempt to redefine this switch status: “the reset switch is turned off.” While a switch may toggle between ON and OFF states, these states must be preceded by relevant actions and desired functions. It is unclear, for example, when the switch was turned OFF, what functions and actions required such state.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing” to Yao et al. (“Yao”).
Examiner’s Note: according to https://ieeexplore.ieee.org/document/10011424, the above cited document has a Date of Publication: 09 January 2023, Publisher: IEEE. And an explanation of this publication date is given: “The Date of Publication for Journals and Standards on IEEE Xplore represents the very first instance of public dissemination.”
As to claim 1, Yao teaches A computation in memory system (As found at least in the Title, Abstract), comprising: a plurality of block pairs (As found in at least FIG. 1, for example: Block A0 and Block B0), wherein each of the plurality of block pairs comprises two types of blocks (As found in at least FIG. 1: labeled Function 1 and Function 2-4), each of the two types of blocks comprises a plurality of operation units (As found in at least FIG. 1: plurality of operation units in Function 1 and Function 2-4), each of the plurality of operation units comprises a static random access memory (SRAM), an AND gate, a NOR gate and a capacitor, the capacitor is electrically connected to the NOR gate, the NOR gate is electrically connected to the AND gate, the AND gate is electrically connected to the SRAM, and the SRAM performs a memory reading and writing function (As found in at least FIG. 1: capacitor Cu connected to NOR gate, NOR gate connected to AND gate, and AND gate connected to SRAM (6T)).
As to claim 2, Yao teaches wherein each of the two types of blocks further comprises a reset switch, two ends of the reset switch are electrically connected to the capacitor and a ground terminal respectively, and the SRAM performs the memory reading and writing function when the reset switch is turned on (As found in at least FIG. 1: under STANDARD R/W: note switch RST is ON; switch RST couples to capacitor Cu and GND, respectively).
As to claim 3, Yao teaches wherein two input terminals of the AND gate are electrically connected to the SRAM and a read-word-line respectively, a control signal is applied to the read-word-line, and the reset switch is turned off, so that the AND gate and the NOR gate perform a bit-level multiply-accumulate operation on data of the SRAM (As found in at least FIG. 1: under 1b x 1b MAC: note switch RST is OFF, AND gate inputs connected to SRAM and RWL, and RWL receives a signal; all this in performing bit-level multiply-accumulate, as found in the Figure itself, the Abstract and under INTRODUCTION).
As to claim 4, Yao teaches wherein two ends of the capacitor are electrically connected to the reset switch and an output terminal of the NOR gate, and two input terminals of the NOR gate are electrically connected to an output terminal of the AND gate and a control line respectively, a control signal is applied to the control line, the reset switch is turned off, so that the NOR gate and the capacitor perform a reference voltage generation (As found in at least FIG. 1: under Vref Generation).
As to claim 5, Yao teaches further comprising: a plurality of comparators (As found in at least FIG. 1: comparators having inputs such as RBL A0 and RBL B0), wherein two input terminals of each of the comparators are electrically connected to the two types of blocks respectively (As found in at least FIG. 1: comparators having inputs such as RBL A0 and RBL B0; inputs connected to two types of blocks, respectively); and a plurality of successive-approximation register (SAR) analog-to-digital (A/D) operation controllers electrically connected to the block pairs respectively (As found in at least FIG. 1: plurality of SAR A/D connected to blocks such as Block A0 and Block B0); also, see at least under: II. RELATED WORKS, A. Multi-Functional CIMC, FIG. 3, B. In-Memory SAR A/D Conversion, etc.), wherein an output terminal of each of the comparators is electrically connected to a corresponding SAR A/D operation controller of the SAR A/D operation controllers (As found in at least FIG. 1).
As to claim 6, Yao teaches wherein the corresponding SAR A/D operation controller repeatedly follows a comparison result from the output terminal of the comparator to successively adjust one block of the two types of blocks for an A/D conversion, wherein a voltage of the one block is higher than a voltage of another block of the two types of blocks (As found in at least FIGS. 1-3: two types of Blocks feed signals to SAR A/D (Successive Approximation Register A/D), and as found in at least FIG. 3, these comparison results are based on a voltage of the one block is higher than a voltage of another block: RBL A0 vs. RBL B0).
As to claim 7, Yao teaches a plurality of distributors electrically connected to the operation units respectively; and an input buffer electrically connected to the distributors (As found in at least FIG. 1: plurality of distributors (unlabeled) connected to at least Block A0 and Block B0, respectively; and input buffer CIM Input Buffer connected to the plurality of distributors).
As to claim 8, Yao teaches a sparsity sensor electrically connected to the input buffer and the SAR A/D operation controllers (As found in at least FIG. 1: Sparsity Sensor), the sparsity sensor detects a sparsity of bit-level inputs in the input buffer, so that the corresponding SAR A/D operation controller scales a dynamic range of the A/D conversion (As found at least in: the title, Abstract, under: I. Introduction, under III. Proposed CIM Architecture, under IV. Embedded Input Sparsity Sensing, etc.).
As to claim 9, Yao teaches an output buffer electrically connected to the SAR A/D operation controllers; and an aggregator electrically connected to the output buffer (As found in at least FIG. 1: CIM Output Buffer and Reconfigurable MAC Aggregator).
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230186979.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827