DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US Pub. 2023/0078456).
Regarding claims 1 and 14, Fig. 1A of Zhang discloses a memory apparatus, comprising:
memory cells [clearly shows in Fig. 2] each connected to one of a plurality of word lines [WL0 to WL15, Fig. 2] and configured to retain a threshold voltage corresponding to one of a plurality of data states [threshold voltages corresponding to data states shows in Fig. 9 to Fig. 11], the plurality of data states including a highest data state [highest state S3, S7, and S15 in Fig. 9, Fig. 10, and Fig. 11 respectively] in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states [threshold of S3 is higher than threshold of S1, S2, threshold of S7 is higher than thresholds of S1 to S6]; and
a control means [controller 150 in Fig. 1B] configured to:
apply each of a series of programming pulses [1302 to 1324] of a program voltage followed by verification pulses [verify voltages are smaller pulses follow right after each program pulse] of a plurality of program verify voltages each associated with one of the plurality of data states to selected ones of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation [clearly shows in Fig. 13], and
skip verification of the memory cells targeted for the highest data state in at least one of the plurality of program loops [as shows in Fig. 13, verify step is skipped for the highest data state 1324, paragraphs 0002 and 0126].
Regarding claims 2, 9, and 15, Fig. 1A of Zhang discloses wherein the memory cells are disposed in memory holes each coupled to one of a plurality of bit lines [BL0 to BL13 in Fig. 2], the memory apparatus further includes a plurality of data latches [latches are within SENSE BLOCK SB1 TO SBp, as shows in Fig. 5] each configured to store data [inherent for latch during writing operation] to be programmed during the program operation and control the one of the plurality of bit lines to allow or inhibit programming of the memory cells of the memory holes coupled to the one of the plurality of bit lines, the plurality of data latches each storing one bit to define bit combinations, and wherein the control means is further configured to: operate and update the plurality of data latches based on the data being programmed [latches temporally stores data for writing or reading operation. New data input will be updated in latches] to the memory cells and the threshold voltage of the memory cells and which of the plurality of data states is being programmed and verified during the program operation [as shows in Fig. 15]; and update the plurality of data latches to track a quantity of subsequent ones of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations [as shows in Fig. 15].
Regarding claims 3, 10, and 16, Fig. 10 of Zhang discloses wherein each of the memory cells is configured to store three bits [8 data] and the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased data state [Er] and a first data state [S1] and a second data state [S2] and a third data state [S3] and a fourth data state [S4] and a fifth data state [S5] and a sixth data state [S6] and a seventh data state [S7], the highest data state being the seventh data state [S7], the plurality of data latches includes a first data latch [550b, Fig. 5] and a second data latch [551b, Fig. 5] and a third data latch [552b, Fig. 5] each configured to store the data to be programmed during the program operation, the plurality of data latches includes a fourth data latch [553b, Fig. 5] configured to control the one of the plurality of bit lines to allow or inhibit programming of the memory cells of the memory holes coupled to the one of the plurality of bit lines [BL0 to BL13, Fig. 2], the bit combinations include sixteen bit combinations [as shows in Fig. 11], and the control means is further configured to: update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch [update new input data for new writing operation] associated with each one of the memory cells targeted for the seventh data state to a first unused one of the sixteen bit combinations in response to the one of the memory cells having the threshold voltage greater than the one of the plurality of program verify voltages associated with the sixth data state [S6] sensed during one of the verification pulses of the one of the plurality of program verify voltages associated with the sixth data state [sixth data state will be verified after programming, because it is sixth data state is not the highest state]; update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch associated with the one of the memory cells targeted for the seventh data state [S7] from the first unused one of the sixteen bit combinations toa second unused one of the sixteen bit combinations following application of a first subsequent one of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state; and update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch associated with the one of the memory cells targeted for the seventh data state [S7] from the second unused one of the sixteen bit combinations to one of the sixteen bit combinations associated with the erased data state [Er] to inhibit programming of the one of the memory cells targeted for the seventh data state following application of a second subsequent one of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data stat [as shows in Fig. 15, only the highest state of a good memory array will skip verifying. The rest of data state will verify after each programming].
Regarding claims 4, 11, and 17, Fig. 13 of Zhang discloses wherein the plurality of data states [as shows in Fig. 10] includes, in order of the threshold voltage increasing in magnitude [as shows in Fig. 10], an erased data state [Er], a next highest data state [S1], and the highest data state [S7], and the control means is further configured to: prior to the next highest data state completing verification, program and verify ones of the memory cells using the series of programming pulses of the program voltage followed by the verification pulses of the plurality of program verify voltages associated therewith and lockout the memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states targeted from further programming [as shows in Fig. 13, each data state is programmed and followed by verify voltage pulses]; following the next highest data state completing verification [verify for S6 state], stop further verification of the ones of the memory cells targeted for the highest data state [no verify after step 1324] and count subsequent ones of the plurality of program loops; and inhibit programming [paragraph 0098] of the ones of the memory cells targeted for the highest data state in response to a quantity of the subsequent ones of the plurality of program loops exceeding a predetermined slow cell count threshold.
Regarding claims 5, 12, and 18, Fig. 10 of Zhang discloses wherein each of the memory cells is configured to store three bits [as shows in Fig. 10] and the plurality of data states includes [S1 to S7], in order of the threshold voltage increasing in magnitude, the erased data state [Er] and a first data state and a second data state and a third data state and a fourth data state and a fifth data state and a sixth data state and a seventh data state [S1 to S7], the next highest data state is the sixth data state [S6] and the highest data state is the seventh data state [S7], and the control means is further configured to: prior to the sixth data state completing verification, program and verify ones of the memory cells targeted for the first data state and the second data state and the third data state and the fourth data state and the fifth data state and the sixth data state and the seventh data state using the series of programming pulses of the program voltage followed by the verification pulses of the plurality of program verify voltages associated therewith and lockout the memory cells having the threshold voltage greater than one of the plurality of verify voltages of the one of the plurality of data states targeted from further programming in response to the ones of the memory cells targeted for the sixth data state and the seventh data state not having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state; following the next highest data state completing verification [as shows in Fig. 13, each state states S1 to S6 are programmed using plurality of programming pulses follows by verify pulses], stop further verification of the ones of the memory cells targeted for the seventh data state and count subsequent ones of the plurality of program loops in response to the ones of the memory cells targeted for the sixth data state and the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state [skip verify for S7 data]; and inhibit programming of the ones of the memory cells targeted for the seventh data state in response to a quantity of the subsequent ones of the plurality of program loops exceeding the predetermined slow cell count threshold [step 1512 and 1514 in Fig. 15].
Regarding claims 6, 13, and 19, Fig. 2 of Zhang discloses wherein the memory cells are disposed in memory holes each coupled to one of a plurality of bit lines [BL0 to BL13], the memory apparatus further includes a plurality of data latches [latches, Fig. 5] each configured to store data to be programmed [latches shows in Fig. 5 are belong to READ/WRITE circuit in Fig. 1A. The latches temporally stores input for programming operation] during the program operation and control the one of the plurality of bit lines to allow or inhibit programming of the memory cells of the memory holes coupled to the one of the plurality of bit lines, the plurality of data latches each storing one bit to define bit combinations, the plurality of data states includes, in order of the threshold voltage increasing in magnitude [as clearly shows in Fig. 10], an erased data state [Er], a next highest data state [S6], and the highest data state [S7, in Fig. 10], and the control means is further configured to: prior to the next highest data state completing verification, program and verify ones of the memory cells using the series of programming pulses of the program voltage followed by the verification pulses of the plurality of program verify voltages associated therewith [clearly shows in Fig. 13] and lockout the memory cells having the threshold voltage [threshold for S7 data state] greater than one of the plurality of verify voltages of the one of the plurality of data states targeted from further programming; and following the next highest data state completing verification, stop further verification of the ones of the memory cells targeted for the highest data state [skip verify for the highest data state] and update the plurality of data latches to track a quantity of subsequent ones of the plurality of program loops for each of the memory cells targeted to be programmed to the highest data state using one or more of the bit combinations.
Regarding claims 7 and 20, Fig. 9 to Fig. 11 of Zhang discloses wherein each of the memory cells is configured to store three bits [Fig. 10] and the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased data state [Er] and a first data state and a second data state and a third data state and a fourth data state and a fifth data state and a sixth data state and a seventh data state [S1 to S7], the highest data state being the seventh data state [S7], the plurality of data latches includes a first data latch and a second data latch and a third data latch [as shows in Fig. 5] each configured to store the data to be programmed during the program operation, the plurality of data latches includes a fourth data latch [as shows in Fig. 5] configured to control the one of the plurality of bit lines to allow or inhibit programming of the memory cells of the memory holes coupled to the one of the plurality of bit lines [as shows in Fig. 2], the bit combinations include sixteen bit combinations [as shows in Fig. 11], and the control means is further configured to: prior to the sixth data state completing verification, update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch associated with each one of the memory cells targeted for the seventh data state to a first unused one of the sixteen bit combinations in response to the one of the memory cells having the threshold voltage greater than the one of the plurality of program verify voltages associated with the sixth data state sensed during one of the verification pulses of the one of the plurality of program verify voltages associated with the sixth data state [as shows in Fig. 13]; prior to the sixth data state completing verification, update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch associated with the one of the memory cells targeted for the seventh data state to one of the sixteen bit combinations associated with the erased data state to inhibit programming of the one of the memory cells targeted for the seventh data state in response to the one of the memory cells having the threshold voltage greater than the one of the plurality of program verify voltages associated with the seventh data state sensed during one of the verification pulses of the one of the plurality of program verify voltages associated with the seventh data state [S7]; prior to the sixth data state completing verification, update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused one of the sixteen bit combinations toa second unused one of the sixteen bit combinations following application of one of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state [as shows in Fig. 13, programming pules follows by verify pulses are applied to program S1 to S6]; following the sixth data state completing verification, update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused one of the sixteen bit combinations from the second unused one of the sixteen bit combinations to one of the sixteen bit combinations associated with the erased data state [Er] to inhibit programming [paragraph 0098] of the one of the memory cells targeted for the seventh data state following application of a first subsequent one of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state and in response to the one of the memory cells targeted for the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state and less than the one of the plurality of verify voltages associated with the seventh data state [S7]; and following the sixth data state completing verification, update at least one of the first data latch and the second data latch and the third data latch and the fourth data latch associated with the one of the memory cells targeted for the seventh data state from the first unused one of the sixteen bit combinations toa second unused one of the sixteen bit combinations following application of a second subsequent one of the series of programming pulses of the program voltage to the one of the memory cells targeted for the seventh data state [using programing pulse 1324 in Fig. 13] and in response to the one of the memory cells targeted for the seventh data state having the threshold voltage greater than the one of the plurality of verify voltages associated with the sixth data state and less than the one of the plurality of verify voltages associated with the seventh data state [no verify for S7 state].
Regarding claim 8, Fig. 1 of Zhang discloses controller [122] in communication with a memory apparatus including memory cells [126] each connected to one of a plurality of word lines [as shows in Fig. 2] and configured to retain a threshold voltage corresponding to one of a plurality of data states [as shows in Fig. 10], the plurality of data states including a highest data state [S7, Fig. 10] in which the threshold voltage of the memory cells associated therewith is higher than for others of the plurality of data states [S1 to S6], the controller configured to:
instruct the memory apparatus to apply each of a series of programming pulses [1032 to 1324] of a program voltage followed by verification pulses [as shows in Fig. 13, each programming pulse except pulse 1324 are followed by verify pulses] of a plurality of program verify voltages each associated with one of the plurality of data states to selected ones of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation [clearly shows in Fig. 13 and Fig. 15]; and
instruct the memory apparatus to skip verification of the memory cells targeted for the highest data state in at least one of the plurality of program loops [as shows in Fig. 13, verify step is skipped for the highest data state 1324, paragraphs 0002 and 0126].
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825